add8616a8a-75b ETC-unknow, add8616a8a-75b Datasheet - Page 7

• Manufacturer Part Number: add8616a8a-75b
• Description: Double Data Rate Sdram
• Manufacturer: ETC-unknow

AC Characteristics
Rev 2 April, 2002
A-Data
Cycle time
Clock high pulse width
Clock low pulse width
Access time form CK to /CK
Data strobe edge to clock edge
Clock to first rising edge of DQS delay
/RAS cycle time
/RAS to /CAS delay
/RAS active time
/RAS precharge time
/RAS to /RAS bank active delay
/CAS to /CAS delay
Data-in setup time (to DQS)
Data-in hold time (to DQS)
DQS Falling Edge to CLK Setup Time
DQS Falling Edge Hold Time from CLK tDSH
Input setup time
Input hold time
DQS-in high level width
DQS-in low level width
Clock to DQS write preamble setup time tWPRES
Write preamble
Data strobe edge to output data edge
Mode register set cycle time
DQS read preamble
System clock
Parameter
/CAS Latency = 2.5
/CAS Latency = 2
tCK2.5
tCK2
tCHW
tCLW
tAC
tDQSCK
tDQSS
tRC
tRCD
tRAS
tRP
tRRD
tCCD
tDS
tDH
tDSS
tIS
tIH
tDSH
tDSL
tWPST
tDQSQ
tMRD
tRPRE
Symbol
7
-0.75
-0.75
0.45
0.45
0.75
0.35
0.35
Min
7.5
7.5
0.5
0.5
0.2
0.2
0.9
0.9
0.4
0.9
65
20
45
20
15
15
1
0
-75BA
120K
Max
0.55
0.55
0.75
0.75
1.25
0.5
1.1
12
12
06
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-0.75
-0.75
0.45
0.45
0.75
0.35
0.35
Min
0.5
0.2
0.2
0.9
0.4
7.5
0.5
0.9
0.9
10
65
20
45
20
15
15
1
0
-75B
120K
Max
0.55
0.55
0.75
0.75
1.25
0.5
1.1
12
12
06
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADD8616A8A
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns