z89138 ZiLOG Semiconductor, z89138 Datasheet - Page 39

• Manufacturer Part Number: z89138
• Description: Voice Processing Controllers
• Manufacturer: ZiLOG Semiconductor

Zilog
DSP Control Register (DSPCON). The DSPCON register
controls various aspects of the Z8 and the DSP. It can con-
figure the internal system clock (SCLK) or the Z8, /RE-
Z8_SCLK
DSP_Reset
DSP_Run
Reserved
DSP_INT2
Z8 IRQ3 (D0). When read, this bit indicates the status of
the Z8 IRQ3. The Z8 IRQ3 is set by the DSP by writing to
D9 of DSP External Register 4 (ICR). By writing a 1 to this
bit, Z8 IRQ3 is Reset.
DSP INT2 (D1). This bit is linked to DSP INT2. Writing a 1
to this bit sets the DSP INT2. Reading this bit indicates the
status of the DSP INT2.
DSP RUN (D4). This bit defines the HALT Mode of the
DSP. If this bit is set to 0, then the DSP clock is turned off
to minimize power consumption. After this bit is set to 1,
then the DSP will continue code execution from where it
was halted. After a hardware reset, this bit is reset to 1.
DS97TAD0201
Z8_IRQ3
DSPCON (F)0CH
Field
76------
--5-----
---4----
----32--
------1-
-------0
Position
Table 9. DSP Control Register (F) OCH [Read/Write]
P R E L I M I N A R Y
Attrib
R/W
R/W
W
W
W
W
R
R
R
R
SET, and HALT of the DSP, and control the interrupt inter-
face between the Z8 and the DSP (Table 9).
DSP RESET (D5). Setting this bit to 1 will reset the DSP.
If the DSP was in HALT Mode, this bit is automatically pre-
set to 1. Writing a 0 has no effect.
Z8 SCLK (D7-D6). These bits define the SCLK frequency
of the Z8. The oscillator can be divided by 8, 4, or 2. After
a reset, both bits default to 00.
Value
00
01
1x
0
1
0
1
1
0
1
0
Voice Processing Controllers
(OSC/8)
(OSC/4)
(OSC/2)
Return “0”
No effect
Reset DSP
Halt_DSP
Run_DSP
No effect
Return “0”
No effect
FB_DSP_INT2
Set DSP_INT2
No effect
FB_Z8_IRQ3
Clear IRQ3
No effect
Z89138/Z89139
Label
39
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