lt6700hdcb-3-trpbf Linear Technology Corporation, lt6700hdcb-3-trpbf Datasheet - Page 11

• Manufacturer Part Number: lt6700hdcb-3-trpbf
• Description: Micropower, Low Voltage, Dual Comparator With 400mv Reference
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
PACKAGE DESCRIPTIO
states on the 0.22µF “integration” capacitor as it remains
balanced at ≈400mV by feedback through the NOT gate.
The input sense voltage, V
current that the NOT gate duty cycle is continually correct-
ing for, thus the digital waveform at the section A com-
parator output is a PWM representation of V
to the 2V “full scale.” In this particular circuit, the PWM
information drives the LED of an optocoupler, allowing the
V
IN
information to be coupled across a dielectric barrier.
3.55 ±0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
2.15 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
U
1.65 ±0.05
(2 SIDES)
U
IN
, is converted to an imbalance
0V TO 2V
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
V
22µF
+
–
IN
1.35 ±0.05
(2 SIDES)
**
††
*
†
10k**
W
1% METAL FILM
DELETE FOR PWM MODE
CONNECT FOR PWM MODE
OPTIMIZED FOR 2kHz ∆Σ SAMPLING, f
0.50 BSC
U
NC7S14
309k*
5 • V
0.25 ± 0.05
0.70 ±0.05
REF
Figure 3. Isolated PWM or ∆Σ Converter
PACKAGE
OUTLINE
IN
= 2V
0.22µF
6-Lead Plastic DFN (2mm × 3mm)
with respect
(Reference LTC DWG # 05-08-1715)
309k*
U
††
(SEE NOTE 6)
470Ω
TOP MARK
100k*
PIN 1 BAR
COIN CELL
Lithium
DCB Package
0.200 REF
412k*
100k*
PWM(MAX)
3V NOM (I
+
+INA
–INB OUTB
LT6700-1
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
≈ 0.6kHz
2.00 ±0.10
GND
(2 SIDES)
TOP AND BOTTOM OF PACKAGE
As an additional option to the circuit, the feedback loop can
be broken and a second optocoupler employed to provide
the charge balance management. This configuration al-
lows for clocking the comparator output (externally to this
circuit) and providing synchronous feedback such that a
simple ∆Σ voltage-to-frequency conversion can be formed
if desired. Approximately 11-bit accuracy and noise per-
formance was observed in a one second integration period
for duty factors from 1% to 99%.
V
LT6700-1/LT6700-2/LT6700-3
S
OUTA
S
< 3mA)
0.1µF
10k
0.1µF
0.75 ±0.05
10k
3.00 ±0.10
(2 SIDES)
6700123 F03
0.00 – 0.05
10k
750Ω
†
1.65 ± 0.10
R = 0.05
(2 SIDES)
6
5
1
2
TYP
SAMPLE
R = 0.115
3V/5V
3V/5V
∆Σ
BOTTOM VIEW—EXPOSED PAD
IN
6
5
1
2
10k
750**
TYP
MOC-207
MOC-207**
PWM OUT
(OR ∆Σ SENSE)
1.35 ±0.10
(2 SIDES)
3
4
6
1
0.50 BSC
0.40 ± 0.10
0.25 ± 0.05
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
(DCB6) DFN 0405
11
6700123fd