ml6460 Micro Electronics Corporation, ml6460 Datasheet - Page 21

• Manufacturer Part Number: ml6460
• Description: Ntsc Video Encoder With Macrovision
• Manufacturer: Micro Electronics Corporation

FUNCTIONAL DESCRIPTION
YDEL1
(B7)
WIDE_VBLANK, B20 Determines which lines to blank
at the beginning of each field. For wide blanking, this bit
is set (B20=1), the ML6460 provides 15 lines of blanking.
For narrow blanking, this bit is cleared (B20=0), the
ML6460 provides 9 lines of blanking.
CC_21, B19 This bit enables (B19=1) and disables
(B19=0) the transmission of closed captioning data on
line 21.
CC_284, B18 This bit enables (B18=1) and disables
(B18=0) the transmission of closed caption data on line
284.
FSYNC, B17 This bit enables (B17=1) and disables
(B17=0) frame syncing.
OVERLAY_ON, B16 This bit enables (B16=1) and
disables (B17=0) the PHERR pin to be used as an
interface to set the internal subcarrier oscillator’s phase
and frequency.
SENSE_HSYNC, B15 This bit selects the polarity of the
HSYNC active edge to a rising edge (if B15=1) or a
falling edge (if B15=0). This bit is active in master
modes or in external slave modes. In internal slave
modes HSYNC is configured as an output to be used for
monitoring purposes. The polarity is still affected by this
bit.
SEL_HSYNC1, B14 This bit, in conjunction with
SEL_HSYNC0 (B13), is used to facilitate pixel
synchronization. Figures 4, 5, 7, and 8 provide a
detailed description. This bit is only active in master
modes or in external slave modes. This bit is de-activated
in internal slave modes.
SEL_HSYNC0, B13 This bit, in conjunction with
SEL_HSYNC1 (B14), is used to facilitate pixel
synchronization. Figures Figures 4, 5, 7, and 8 provide a
detailed description. This bit is only active in master
modes or in external slave modes. This bit is de-activated
in internal slave modes.
SWITCH_UV, B12 This bit is used to switch Cr and Cb
internally when set (B12=1). This bit is cleared (B12=0)
for normal operation. This bit is intended for debug
purposes only. If used, there may be some slight artifacts
at the end of active line.
0
0
1
1
YDEL0
(B6)
Table 5. Luma Delay Selection
0
1
0
1
OPERATION
Normal
Delay Luma Channel by 1 TCLK
Advance Luma Channel by 1 TCLK
Advance Luma Channel by 2 TCLK
(Continued)
SWITCH_FIELD, B11 This bit is used to switch even/odd
fields when set (B11=1). This bit is cleared (B12=0) for
normal operation. This bit is only active in internal slave
mode.
SENSE_VSYNC, B10 This bit selects the polarity of the
VSYNC active edge to a rising edge (if B10=1) or a
falling edge (if B10=0). In internal slave modes VSYNC
is configured as an output to be used for monitoring
purposes. The polarity is still affected by this bit.
FLD_FRM_MODE, B9 When set (B9=1), it causes the
ML6460 FIELD pin to give analog field information if the
FIELD pin is configured as an output (see B8). When
cleared (B9=0), it causes the field pin to give odd/even
field information if the FIELD pin is configured as an
output (see B8).
FRAME_MODE, B8 This bit configures the FIELD pin of
the ML6460 as an input (if B8=1) or as an output (if
B8=0).
YDEL1, B7 This bit, in conjunction with YDEL0 (B6), is
used to select luma delay in order to align luma and
chroma data. See Table 5.
YDEL0, B6 This bit, in conjunction with YDEL1 (B7), is
used to select luma delay in order to align luma and
chroma data. See Table 5.
BURST_ON, B5 When active (B5=1) this bit provides
burst at all times for testing purposes only. For normal
operation this bit is cleared (B5=0).
ACTIVE_ON, B4 When active (B4=1) this bit eliminates
horizontal and vertical blanking intervals. Burst is
suppressed. For testing purposes only. For normal
operation this bit is cleared (B4=0).
FIX_SCH, B3 When active (B3=1) this bit maintains
SCH phase. In this condition known as a “coherent
subcarrier” such that the subcarrier has a known phase
relative to the active edge of HSYNC pulse. When this
bit is cleared (B3=0), the subcarrier generation block is in
free run mode. This condition is known as “incoherent
subcarrier” where the phase of the subcarrier relative to
the HSYNC is not fixed.
CC_ALL, B2 When active (B2=1) this bit enables closed
caption transmission on every line. For testing purposes
only. For normal operation this bit is cleared (B2=0) and
closed caption is enabled through control register bits
CC_21 (B19) and CC_284 (B18).
SUBCARRIER_OFF, B1 When active (B1=1) this bit
disables the internal subcarrier oscillator. Used for test
purposes only. For normal operation this bit is cleared
(B1=0).
AC_DC, B0 This bit configures the output buffers for AC
coupled drive (if B0=1) and DC couple drive (if B0=0).
ML6460
21