ml6461 Micro Electronics Corporation, ml6461 Datasheet - Page 19

• Manufacturer Part Number: ml6461
• Description: Ntsc Video Encoder
• Manufacturer: Micro Electronics Corporation

FUNCTIONAL DESCRIPTION
BLANK
SYNC
LEVEL
BLANK
SYNC
LEVEL
LEVEL
selects between internal (B26=1) and external slave
modes (B26=0).
SELCCIR, B27 This bit determines the frequency of
choice between CCIR656 clock rate(27MHz) and Square
Pixel clock rate (24.54MHz). When this bit is set (B27=1),
CCIR656 clock rate is selected. When this bit is cleared
(B27=0), the Square Pixel clock rate is selected.
SLAVE_MODE, B26 This bit determines the choice of
two slave modes: internal slave mode or external slave
mode. In internal slave mode (B26=1), horizontal and
vertical timing information is embedded in the YCrCb
data (via SAV / EAV codes); while the HSYNC and
VSYNC pins can be used as outputs. In external slave
mode (B26=0), horizontal and vertical sync pulses must
LEVEL
50 ±2 IRE
50 ±2 IRE
40 IRE
40 IRE
Closed Caption on Line21
[CC_21 = 1 and CC_284 = 0]
±0.25µs
±0.25µs
3.58MHz
±0.25µs
±0.25µs
10.003
3.58MHz
10.003
COLOR
COLOR
BURST
BURST
10.5
10.5
27.382µs
27.382µs
7 CYCLES
7 CYCLES
12.91µs
12.91µs
A
R
S
T
T
A
R
S
T
T
TWO: 7 BIT + PARITY BIT
Figure 13. Closed Caption on Line 21 and Line 284.
TWO: 7 BIT + PARITY BIT
A0 ~ A6
A0 ~ A6
33.764µs
33.764µs
LINE 21
LINE 21
A7
A7
(Continued)
A8 ~ A14
A8 ~ A14
Closed Caption on Line21 and Line 284
[CC_21 = 1 and CC_284 = 1]
A15
A15
LEVEL
BLANK
SYNC
LEVEL
BLANK
SYNC
LEVEL
LEVEL
50 ±2 IRE
50 ±2 IRE
be provided for timing and synchronization;in this case
HSYNC and VSYNC pins are inputs. See Table 3.
HRESET_MODE, B25 This bit determines whether the
HSYNC is given at the beginning of active video (B25=1)
or HSYNC is given at the beginning of blanking (B25=0).
This bit (B25) is only available for external slave modes.
ANALOG_HBLANK, B24 This bit determines whether
the ML6461 is to encode for ITU_R656_compliant
"digital" or ITU_/SMPTE_compliant "analog" encoding
specifications. When this bit is cleared (B24=0), the
ML6461 is optimized for full "digital" line encoding,
where the number of active pixels is 720 for CCIR656
rates and 640 for square pixel rates. No tapering (edge
40 IRE
40 IRE
Closed Caption on Line284
[CC_21 = 0 and CC_284 = 1]
±0.25µs
3.58MHz
±0.25µs
±0.25µs
3.58MHz
±0.25µs
10.003
10.003
COLOR
COLOR
BURST
BURST
10.5
10.5
27.382µs
27.382µs
7 CYCLES
7 CYCLES
12.91µs
12.91µs
A
T
A
R
T
S
T
R
T
S
TWO: 7 BIT + PARITY BIT
A16 ~ A22
TWO: 7 BIT + PARITY BIT
A0 ~ A6
33.764µs
LINE 284
33.764µs
LINE 284
A7
A23
ML6461
A8 ~ A14
A24 ~ A30
A15
A31
19