74lcxh162373 Fairchild Semiconductor, 74lcxh162373 Datasheet

74lcxh162373

Manufacturer Part Number

74lcxh162373

Description

Low Voltage 16-bit Transparent Latch With Bushold And 26 ?series Resistor Outputs

Manufacturer

Fairchild Semiconductor

Datasheet

1.74LCXH162373.pdf (11 pages)

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74LCXH162373GX

(Note 1)

74LCXH162373MEA

74LCXH162373MEX

74LCXH162373MTD

74LCXH162373MTX

74LCXH162373

Low Voltage 16-Bit Transparent Latch

with Bushold and 26

General Description

The LCXH162373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear transparent to the data when the Latch Enable (LE)

is HIGH. When LE is LOW, the data that meets the setup

time is latched. Data appears on the bus when the Output

Enable (OE) is LOW. When OE is HIGH, the outputs are in

a high impedance state.

The LCXH162373 is designed for low voltage (2.5V or

3.3V) V

signal environment. The 26

output overshoot and undershoot.

The LCXH162373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

The LCXH162373 data inputs include active bushold cir-

cuitry, eliminating the need for external pull-up resistors to

hold unused or floating data inputs at a valid logic level.

Ordering Code:

Note 1: BGA package available in Tape and Reel only.

Logic Symbol

Order Number

applications with capability of interfacing to a 5V

(Preliminary)

Package

Number

BGA54A

MS48A

MTD48

series resistor helps reduce

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

[RAIL]

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

[TAPE and REEL]

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[RAIL]

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TAPE and REEL]

DS500445

Series Resistor Outputs

Features

5V tolerant control inputs and outputs

2.3V–3.6V V

Equivalent 26 series resistors on outputs

Bushold on inputs eliminates the need for external

pull-up/pull-down resistors

6.2 ns t

Power down high impedance inputs and outputs

Implements patented noise/EMI reduction circuitry

Latch-up performance exceeds 500 mA

ESD performance:

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

12 mA output drive (V

Human body model

Machine model

Package Description

max (V

specifications provided

200V

3.3V), 20 A I

2000V

3.0V)

February 2001

Revised March 2002

www.fairchildsemi.com

max

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74lcxh162373 Summary of contents

Page 1

... Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [RAIL] 74LCXH162373MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 74LCXH162373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [RAIL] 74LCXH162373MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6 ...

Page 2

Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW Latch Enable Input n I –I Inputs (Bushold ...

Page 3

Functional Description The LCXH162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following ...

Page 4

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current ...

Page 5

DC Electrical Characteristics Symbol Parameter I Bushold Input Minimum I(HOLD) Drive Hold Current I Bushold Input Over-Drive I(OD) Current to Change State I 3-STATE Output Leakage OZ I Power-Off Leakage Current OFF I Quiescent Supply Current CC I Increase in ...

Page 6

Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP OL V Quiet Output Dynamic Valley V OLV OL Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT C Power Dissipation Capacitance PD www.fairchildsemi.com Conditions C ...

Page 7

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C Test PLH PZL PZH Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable ...

Page 8

Schematic Diagram Generic for LCX Family www.fairchildsemi.com 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide www.fairchildsemi.com Package Number MS48A 10 ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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