74abt273cmtcx-nl Fairchild Semiconductor, 74abt273cmtcx-nl Datasheet

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74abt273cmtcx-nl

Manufacturer Part Number
74abt273cmtcx-nl
Description
Octal D-type Flip-flop
Manufacturer
Fairchild Semiconductor
Datasheet
© 2005 Fairchild Semiconductor Corporation
74ABT273CSC
74ABT273CSJ
74ABT273CMSA
74ABT273CMTC
74ABT273CMTCX_NL
(Note 1)
74ABT273
Octal D-Type Flip-Flop
General Description
The ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Order Number
Package
Number
MSA20
MTC20
MTC20
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
DS011549
Features
Pin Descriptions
Eight edge-triggered D-type flip-flops
Buffered common clock
Buffered, asynchronous Master Reset
See ABT377 for clock enable version
See ABT373 for transparent latch version
See ABT374 for 3-STATE version
Output sink capability of 64 mA, source capability of
32 mA
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Non-destructive hot insertion capability
Disable time less than enable time to avoid bus conten-
tion
D
MR
CP
Q
Pin Names
0
0
–D
–Q
Package Description
7
7
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
January 1993
Revised March 2005
Description
www.fairchildsemi.com

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74abt273cmtcx-nl Summary of contents

Page 1

... MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ABT273CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ABT273CMTCX_NL MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. ...

Page 2

Truth Table Operating Mode Reset (Clear) Load “1” Load “0” H HIGH Voltage Level steady state h HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L LOW Voltage Level steady state I LOW Voltage Level one ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 3)  Input Current (Note Voltage Applied to Any Output in the Disabled ...

Page 4

AC Electrical Characteristics (SSOIC package) Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH PHL n t Propagation Delay PHL Operating Requirements Symbol Parameter t (H) Setup Time, HIGH ...

Page 5

AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Amplitude 3.0V FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay, Pulse Width Waveforms FIGURE 5. 3-STATE Output HIGH and LOW Enable and Disable ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide www.fairchildsemi.com Package Number M20B 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide www.fairchildsemi.com Package Number MSA20 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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