74abt541cmsax-nl Fairchild Semiconductor, 74abt541cmsax-nl Datasheet

no-image

74abt541cmsax-nl

Manufacturer Part Number
74abt541cmsax-nl
Description
74abt541 Octal Buffer/line Driver With 3-state Outputs
Manufacturer
Fairchild Semiconductor
Datasheet
©1992 Fairchild Semiconductor Corporation
74ABT541 Rev. 1.4
74ABT541
Octal Buffer/Line Driver with 3-STATE Outputs
Features
Ordering Information
Devices also available in Tape and Reel. Specify by appending suffix “X” to the ordering number.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
74ABT541CSC
74ABT541CSJ
74ABT541CMSA
74ABT541CMTC
Order Number
Non-inverting buffers
Output sink capability of 64mA, source capability of
32mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50pF and 250pF
loads
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Guaranteed latchup protection
High-impedance, glitch-free bus loading during entire
power up and power down cycle
Nondestructive, hot-insertion capability
Flow-through pinout for ease of PC board layout
Disable time less than enable time to avoid bus
contention
Package
Number
MSA20
MTC20
M20D
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
General Description
The ABT541 is an octal buffer and line driver with
3-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus-oriented trans-
mitter/receiver. The ABT541 is similar to the ABT244
with broadside pinout.
Pin Descriptions
OE
I
O
0
–I
Pin Names
0
–O
1
7
Package Description
, OE
7
2
Output Enable Input (Active LOW)
Inputs
Outputs
Description
www.fairchildsemi.com
March 2007
tm

Related parts for 74abt541cmsax-nl

74abt541cmsax-nl Summary of contents

Page 1

... MTC20 Devices also available in Tape and Reel. Specify by appending suffix “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram ©1992 Fairchild Semiconductor Corporation 74ABT541 Rev. 1.4 General Description The ABT541 is an octal buffer and line driver with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented trans- mitter/receiver ...

Page 2

... Symbol T Free Air Ambient Temperature A V Supply Voltage CC ∆ ∆ t Minimum Input Edge Rate Data Input Enable Input ©1992 Fairchild Semiconductor Corporation 74ABT541 Rev. 1.4 Outputs Parameter Parameter 2 Rating –65°C to +150°C – ...

Page 3

... Outputs Enabled CCT I /Input CC Outputs 3-STATE Outputs 3-STATE I Dynamic I No Load CCD CC Notes: < 0.8mA/MHz. 2. For 8-bit toggling, I CCD 3. Guaranteed, but not tested. ©1992 Fairchild Semiconductor Corporation 74ABT541 Rev. 1.4 V Conditions CC Recognized HIGH Signal Recognized LOW Signal = –18mA Min –3mA Min –32mA I ...

Page 4

... AC Electrical Characteristics SOIC and SSOP package. Symbol Parameter t Propagation Delay, PLH Data to Outputs t PHL t Output Enable Time PZH t PZL t Output Disable Time PHZ t PLZ ©1992 Fairchild Semiconductor Corporation 74ABT541 Rev. 1.4 Conditions = 50pF 500Ω 25°C (4) 5 25°C (4) 5.0 ...

Page 5

... LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. 10. The 3-STATE delays are dominated by the RC network (500Ω, 250pF) on the output and have been excluded from the datasheet. ©1992 Fairchild Semiconductor Corporation 74ABT541 Rev. 1.4 = –40°C to +85°C, –40°C to +85°C, ...

Page 6

... Capacitance Symbol Parameter C Input Capacitance IN (16) C Output Capacitance OUT Note: is measured at frequency MHz, per MIL-STD-883, Method 3012. 16. C OUT ©1992 Fairchild Semiconductor Corporation 74ABT541 Rev. 1.4 = –40°C to +85°C, = –40°C to +85° 4.5V to 5.5V, = 4.5V to 5.5V 50pF, ...

Page 7

... Figure 1. Standard AC Test Load Amplitude 3.0V AC Waveforms Figure 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions Figure 5. Propagation Delay, Pulse Width Waveforms ©1992 Fairchild Semiconductor Corporation 74ABT541 Rev. 1.4 Figure 2. Test Input Signal Levels Rep. Rate MHz 500 ns 2 ...

Page 8

... Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 8. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide ©1992 Fairchild Semiconductor Corporation 74ABT541 Rev. 1.4 Package Number M20B 8 www.fairchildsemi.com ...

Page 9

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 9. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1992 Fairchild Semiconductor Corporation 74ABT541 Rev. 1.4 Package Number M20D 9 www.fairchildsemi.com ...

Page 10

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 10. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide ©1992 Fairchild Semiconductor Corporation 74ABT541 Rev. 1.4 Package Number MSA20 10 www.fairchildsemi.com ...

Page 11

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 11. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1992 Fairchild Semiconductor Corporation 74ABT541 Rev. 1.4 Package Number MTC20 11 www.fairchildsemi.com ...

Page 12

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world. ActiveArray Bottomless Build it Now CoolFET CROSSVOLT CTL™ Current Transfer Logic™ ...

Related keywords