DM74S174N Fairchild Semiconductor, DM74S174N Datasheet
DM74S174N
Specifications of DM74S174N
74S174N
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DM74S174N Summary of contents
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... When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output. Ordering Code: Order Number Package Number DM74S174N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74S175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide ...
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Function Table (Each Flip-Flop) Clear HIGH Level (steady state) L LOW Level (steady state) X Don’t Care Transition from LOW-to-HIGH level Q The level of Q before the indicated steady-state input conditions were established. 0 ...
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Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...
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Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter V Input Clamp Voltage I V HIGH Level OH Output Voltage V LOW Level OL Output Voltage I Input Current @ Max Input Voltage I I HIGH ...
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Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...