dm74s163 Fairchild Semiconductor, dm74s163 Datasheet
dm74s163
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dm74s163 Summary of contents
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... DM74S161 • DM74S163 Synchronous 4-Bit Binary Counters General Description These synchronous, presettable counters feature an inter- nal carry look-ahead for application in high-speed counting designs. They are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchro- ...
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... Logic Diagram www.fairchildsemi.com DM74S161 • DM74S163 2 ...
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Timing Diagram Sequence: 1. Clear outputs to zero 2. Preset to binary twelve 3. Count to thirteen, fourteen, fifteen, zero, one and two 4. Inhibit 3 www.fairchildsemi.com ...
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Parameter Measurement Information Note A:The input pulses are supplied by generators having the following characteristics: PRR 1 MHz, duty cycle 50 For DM74S161/163, t OUT Note B: Outputs Q and carry are tested for ...
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... Note 4: Applies only to the DM74S163 which has synchronous clear inputs. Note 5: Applies only to the DM74S161 which has asynchronous clear inputs. (Note 1) Note 1: The “Absolute Maximum Ratings” are those values beyond which 7V the safety of the device cannot be guaranteed. The device should not be operated at these limits ...
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... PHL HIGH-to-LOW Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output (Note 8) Note 8: Propagation delay for clearing is measured from clear input for the DM74S161 and from the clock input transition for the DM74S163. www.fairchildsemi.com Conditions Min Min ...
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Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...