74alvch16373dl NXP Semiconductors, 74alvch16373dl Datasheet - Page 2

• Manufacturer Part Number: 74alvch16373dl
• Description: 2.5v/3.3v 16-bit D-type Transparent Latch 3-state
• Manufacturer: NXP Semiconductors

1. C
Philips Semiconductors
FEATURES
DESCRIPTION
The 74ALVCH16373 is a 16-bit D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for bus
oriented applications. Incorporates bus hold data inputs which
eliminate the need for external pull-up or pull-down resistors to hold
unused inputs. One latch enable (LE) input and one output enable
(OE) are provided per 8-bit section.
The 74ALVCH16373 consists of 2 sections of eight D-type
transparent latches with 3-State true outputs. When LE is HIGH,
data at the Dn inputs enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
QUICK REFERENCE DATA
GND = 0V; T
NOTE:
ORDERING INFORMATION
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
1999 Sep 20
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
Low inductance multiple V
and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50 transmission lines @ 85 C
Current drive 24 mA at 3.0 V
16-bit D-type transparent latch (3-State)
t
t
C
C
C
PHL
P
f
SYMBOL
o
I
PD
PD
D
= output frequency in MHz; V
= C
/t
/t
PLH
is used to determine the dynamic power dissipation (P
PD
amb
PACKAGES
TM
V
= 25 C; t
CC
flow-through standard pin-out architecture
Propagation delay
Dn to Qn
Propagation delay
LE to Qn
Input capacitance
Power dissipation capacitance per latch
Power dissipation capacitance per latch
2
f
i
g
g
+
r
= t
CC
(C
f
L
and ground pins for minimum noise
2.5ns
PARAMETER
V
CC
y
y
CC
= supply voltage in V;
2
TEMPERATURE RANGE
f
o
) where: f
–40 C to +85 C
–40 C to +85 C
i
= input frequency in MHz; C
D
(C
in W):
L
V
V
V
V
V = GND to V
V
CC
CC
CC
CC
I
= GND to V
OUTSIDE NORTH AMERICA
V
CC
= 2.5V, C
= 3.3V, C
= 2.5V, C
= 3.3V, C
2
74ALVCH16373 DGG
2
74ALVCH16373 DL
PIN CONFIGURATION
f
o
) = sum of outputs.
L
L
L
L
CC
CC
= 30pF
= 50pF
= 30pF
= 50pF
1
1
L
CONDITIONS
= output load capacitance in pF;
GND
GND
GND
GND
1OE
1Q4
1Q5
2Q3
2Q4
2Q6
2Q7
2OE
1Q0
1Q1
1Q2
1Q3
V
1Q6
1Q7
2Q0
2Q1
2Q2
V
2Q5
CC
CC
Outputs disabled
Outputs enabled
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
NORTH AMERICA
ACH16373 DGG
ACH16373 DL
SW00066
74ALVCH16373
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TYPICAL
1LE
1D0
1D1
GND
1D2
1D3
V
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
V
2D4
2D5
GND
2D6
2D7
2LE
Product specification
CC
CC
2.1
2.1
2.2
2.2
5.0
16
10
DWG NUMBER
853-2086 22418
SOT370-1
SOT362-1
UNIT
pF
pF
pF
ns
ns