74alvcf162835t Fairchild Semiconductor, 74alvcf162835t Datasheet
74alvcf162835t
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74alvcf162835t Summary of contents
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... CMOS power dissipation. Ordering Code: Package Order Number Number 74ALVCF162835T MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation ...
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Connection Diagram Logic Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) LE Latch Enable Input CLK Clock Input Data Inputs 3-STATE Outputs 1 18 Truth Table Inputs ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( − 0. Output Voltage (V ) (Note Input Diode Current ( < Output Diode Current ...
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AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX Propagation Delay PHL PLH Bus-to-Bus Propagation Delay PHL PLH Clock to Bus Propagation Delay PHL PLH LE to Bus t , ...
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Characteristics OUT OUT FIGURE 1. Characteristics for Output - Pull Up Drive FIGURE 2. Characteristics for Output - Pull Down Driver I versus versus www.fairchildsemi.com ...
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AC Loading and Waveforms FIGURE 3. AC Test Circuit ( Input Charactertistics 1MHz; t Symbol 3.3V ± 0. − 0. ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...