74alvc573 NXP Semiconductors, 74alvc573 Datasheet

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74alvc573

Manufacturer Part Number
74alvc573
Description
Octal D-type Transparent Latch 3-state
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for
each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input
and an outputs enable (OE) input are common to all latches.
When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this
condition, the latches are transparent, that is, a latch output will change each time its
corresponding D-input changes. When pin LE is LOW, the latches store the information
that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of
pin LE.
When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins
Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of input pin OE does not affect the state of the latches.
The 74ALVC573 is functionally identical to the 74ALVC373, but has a different pin
arrangement.
74ALVC573
Octal D-type transparent latch; 3-state
Rev. 03 — 26 October 2007
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
ESD protection:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A 115-A exceeds 200 V
Product data sheet

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74alvc573 Summary of contents

Page 1

... When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latches. The 74ALVC573 is functionally identical to the 74ALVC373, but has a different pin arrangement. 2. Features Wide supply voltage range from 1 ...

Page 2

... Q7 mna807 Fig 2. IEC logic symbol LATCH Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state 0. EN1 mna808 3-STATE 15 ...

Page 3

... Product data sheet LATCH LATCH Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state Q mna189 LATCH LATCH LATCH ...

Page 4

... Fig 7. Pin configuration DHVQFN20 Description data input latch enable input (active HIGH) output enable input (active LOW) 3-state latch output supply voltage ground (0 V) Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state terminal 1 index area ...

Page 5

... > < output HIGH or LOW state output 3-state power-down mode +85 C amb Rev. 03 — 26 October 2007 74ALVC573 Internal latch Output Min Max Unit 0.5 +4.6 V ...

Page 6

... GND CC I Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state Min Max 1.65 3 3 +85 C [1] Min Typ ...

Page 7

... Qn; see Figure Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state +85 C [1] Min Typ - 0.1 - 0 amb 12 +85 C [1] Min Typ [2] 1 ...

Page 8

... per latch GND outputs HIGH or LOW state outputs 3-state = 25 C amb in W where Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state Figure 12 +85 C Min Typ 3.8 3.3 3.3 3.3 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.7 [ ...

Page 9

... 1/f max GND PHL Table 8. Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state t PLH mna811 PLH mna812 © NXP B.V. 2007. All rights reserved ...

Page 10

... Table GND GND Table 8. Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state t PZL PZH V M outputs outputs enabled disabled mna813 mna814 © NXP B.V. 2007. All rights reserved ...

Page 11

... DUT R T Load Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state EXT 001aae331 of the pulse generator EXT ...

Page 12

... 0.49 0.32 13.0 7.6 10.65 1.27 0.36 0.23 12.6 7.4 10.00 0.019 0.013 0.51 0.30 0.419 0.05 0.014 0.009 0.49 0.29 0.394 REFERENCES JEDEC JEITA MS-013 Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state detail 1.1 1.1 1.4 0.25 0.25 0.4 1.0 0.043 0.043 0.055 0.01 0.01 ...

Page 13

... Product data sheet 2.5 scale (1) ( 0.30 0.2 6.6 4.5 0.65 0.19 0.1 6.4 4.3 REFERENCES JEDEC JEITA MO-153 Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN ...

Page 14

... 2.5 scale (1) ( 4.6 3.15 2.6 1.15 0.5 3.5 4.4 2.85 2.4 0.85 REFERENCES JEDEC JEITA MO-241 - - - Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state detail 0.5 0.05 0.1 0.1 0.05 0.3 EUROPEAN PROJECTION SOT764-1 ...

Page 15

... DHVQFN20 package added. 8: derating values added for DHVQFN20 package. 12: outline drawing added for DHVQFN20 package. Product specification Product specification Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state Change notice Supersedes - 74ALVC573_2 - 74ALVC573_1 - - © NXP B.V. 2007. All rights reserved ...

Page 16

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 26 October 2007 74ALVC573 Octal D-type transparent latch; 3-state © NXP B.V. 2007. All rights reserved ...

Page 17

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 26 October 2007 Document identifier: 74ALVC573_3 ...

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