24lc22a Microchip Technology Inc., 24lc22a Datasheet - Page 6

• Manufacturer Part Number: 24lc22a
• Description: 2k Vesa E-edid? Serial Eeprom
• Manufacturer: Microchip Technology Inc.

24LC22A
FIGURE 3-3:
DS21683B-page 6
Note 1: The base flowchart is copyright © 1993, 1994, 1995 Video Electronic Standard Association (VESA) from
DDC Circuit Powered
Display Power-on
2: The dash box and text “The 24LC21A and... inside dash box.” are added by Microchip Technology Inc.
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LCS22A.
from +5 volts
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
or
No
No
No
DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA
No
Switch to DDC2™ mode.
Send EDID continuously
Reset Vsync counter = 0
Increment VCLK counter
Switch back to DDC1™
Set Vsync counter = 0
using Vsync as clock
Stop sending EDID.
transition on SCL
Communication
Counter=128 or
DDC2 address
transition state
(if appropriate)
timer expired?
SCL, SDA or
or start timer
VCLK lines?
High-to-Low
transition on
Display has
Change on
Yes
received?
Is Vsync
present?
High-low
optional
VCLK
cycle?
mode.
SCL?
is idle
Valid
?
?
Yes
Yes
Yes
Yes
No
Yes
Yes
No
No
Yes
No
Reset counter or timer
specification to determine
idle. Display waiting for
DDC2 communication
The 24LC22A was designed to
comply to the portion of flowchart inside dash box.
See Access.bus
correct procedure.
Valid Access.bus
Access.busTM
address byte.
High-to-Low
transition on
received?
Is display
address?
capable?
address
DDC2B
SCL?
No
Yes
Yes
Yes
No
No
© 2007 Microchip Technology Inc.
Yes
No
Respond to DDC2B
Receive DDC2B
command
command
®