24lc64f Microchip Technology Inc., 24lc64f Datasheet - Page 10
24lc64f
Manufacturer Part Number
24lc64f
Description
64k I 2 C? Serial Eeprom With Quarter-array Write-protect
Manufacturer
Microchip Technology Inc.
Datasheet
1.24LC64F.pdf
(30 pages)
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24AA64F/24LC64F
7.0
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally-timed write cycle and ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be re-sent. If the cycle is complete, the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 7-1 for a
flow diagram of this operation.
DS22154A-page 10
ACKNOWLEDGE POLLING
FIGURE 7-1:
Initiate Write Cycle
Send Control Byte
Write Command
with R/W = 0
Condition to
Acknowledge
Send Stop
Send Start
Did Device
(ACK = 0)?
Operation
Send
Next
ACKNOWLEDGE POLLING
FLOW
© 2009 Microchip Technology Inc.
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