25lc128 Microchip Technology Inc., 25lc128 Datasheet - Page 12
25lc128
Manufacturer Part Number
25lc128
Description
128k Spi Bus Serial Eeprom
Manufacturer
Microchip Technology Inc.
Datasheet
1.25LC128.pdf
(26 pages)
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25AA128/25LC128
2.7
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
• After a byte write, page write or STATUS register
• CS must be set high after the proper number of
• Access to the array during an internal write cycle
TABLE 2-4:
DS21831C-page 12
x = don’t care
the write enable latch
write, the write enable latch is reset
clock cycles to start an internal write cycle
is ignored and programming is continued
(SR bit 1)
WEL
0
1
1
1
Data Protection
WRITE-PROTECT FUNCTIONALITY MATRIX
(SR bit 7)
WPEN
x
0
1
1
1 (high)
0 (low)
(pin 3)
WP
x
x
Protected Blocks
Protected
Protected
Protected
Protected
2.8
The 25XX128 powers on in the following state:
• The device is in low-power Standby mode
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
(CS = 1)
enter active state
Unprotected Blocks
Power-On State
Protected
Writable
Writable
Writable
© 2007 Microchip Technology Inc.
STATUS Register
Protected
Protected
Writable
Writable