is62c1024-35wi ETC-unknow, is62c1024-35wi Datasheet
is62c1024-35wi
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is62c1024-35wi Summary of contents
Page 1
... CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62C1024 is available in 32-pin 600mil DIP, 450mil SOP and 8*20mm TSOP-1 packages. DECODER MEMORY ARRAY ...
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... IS62C1024 PIN CONFIGURATION 32-Pin SOP and DIP VCC A16 2 31 A15 A14 3 30 CE2 A12 A13 A11 A10 CE1 I/O7 I/ I/O6 I/ I/O5 I/ I/O4 GND 16 17 I/O3 PIN DESCRIPTIONS A0-A16 ...
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... IS62C1024 ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation Output Current (LOW) OUT Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... IS62C1024 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CE1 Access Time t 1 ACE t CE2 Access Time ACE 2 OE Access Time t DOE OE to Low-Z Output (2) t LZOE OE to High-Z Output (2) t HZOE ...
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... IS62C1024 AC WAVEFORMS READ CYCLE NO. 1 (1,2) ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCE HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = V 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. ...
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... IS62C1024 WRITE CYCLE SWITCHING CHARACTERISTICS Power) Symbol Parameter t Write Cycle Time WC CE1 to Write End t SCE 1 t CE2 to Write End 2 SCE t Address Setup Time to Write End AW t Address Hold from Write End HA t Address Setup Time SA WE Pulse Width (4) t PWE t Data Setup to Write End ...
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... IS62C1024 CE1 CE1 WRITE CYCLE NO. 2 (CE1 CE1 CE1, CE2 Controlled) ADDRESS OE CE LOW DATA UNDEFINED OUT D IN Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write ...
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... DIP 70 IS62C1024-70Q 450mil SOP 70 IS62C1024-70T 8*20mm TSOP-1 NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, 8 ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 35 IS62C1024-35WI 600mil DIP 35 IS62C1024-35QI 450mil SOP 35 IS62C1024-35TI 8*20mm TSOP-1 45 IS62C1024-45WI 600mil DIP 45 IS62C1024-45QI 450mil SOP 45 IS62C1024-45TI ...