is42s16400d-die Integrated Silicon Solution, Inc., is42s16400d-die Datasheet
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is42s16400d-die
Manufacturer Part Number
is42s16400d-die
Description
1 Meg Bits X 16 Bits X 4 Banks 64-mbit Synchronous Dynamic Ram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
1.IS42S16400D-DIE.pdf
(1 pages)
IS42S16400D-DIE
FEATURES
• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to a
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
• Programmable burst sequence:
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Burst termination by burst stop and precharge
• Byte controlled by LDQM and UDQM
PIN DESCRIPTIONS
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. 00A
11/22/06
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
A0-A11
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
WE
LDQM
UDQM
V
positive clock edge
– (1, 2, 4, 8, full page)
Sequential/Interleave
operations capability
command
DD
Address Input
Bank Select Address
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
Write Enable
Upper Bye, Input/Output Mask
Power
Data I/O
Lower Bye, Input/Output Mask
1-800-379-4774
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42S16400D is organized
as 1,048,576 bits x 16-bit x 4-bank for improved performance.
The synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input. Note: This is a
summary datasheet specific to the die format. Please refer
to the IS42S16400D for complete device specifications.
KEY TIMING PARAMETERS
BONDING DIAGRAM
Parameter
Clk Cycle Time
Clk Frequency
Access Time from Clock
GND
V
GND
NC
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
DD
Y
(0,0)
Q
Q
Bonding Pads
PRELIMINARY INFORMATION
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
Burn-in Pads
41
53
1
13
DECEMBER 2006
166
133
7.5
-6
6
5
6
ISSI
39
36
35
28
27
15
143
133
7.5
5.4
-7
7
6
Unit
X
Mhz
Mhz
ns
ns
ns
ns
®
1