mt29f2g16abdhc-et Micron Semiconductor Products, mt29f2g16abdhc-et Datasheet - Page 31

• Manufacturer Part Number: mt29f2g16abdhc-et
• Description: 2gb, 4gb, 8gb X8, X16 Nand Flash Memory
• Manufacturer: Micron Semiconductor Products

BLOCK ERASE Operation
BLOCK ERASE 60h-D0h
Figure 24:
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7
2_4_8gb_nand_m49a__2.fm - Rev. D 12/06 EN
WE#
R/B#
I/Ox
ALE
CE#
RE#
CLE
60h
BLOCK ERASE Operation
Address input (3 cycles)
Erasing occurs at the block level. For example, the MT29F2G08xxC device has 2,048
erase blocks organized into 64 pages per block, 2,112 bytes per page (2,048 + 64 bytes).
Each block is 132K bytes (128K + 4K bytes). The BLOCK ERASE command operates on
one block at a time (see Figure 24).
Three cycles of addresses BA[17:6] and PA[5:0] are required. Although page addresses
PA[5:0] are loaded, they are “Don’t Care” and are ignored for BLOCK ERASE operations.
See Table 4 on page 12 for addressing details.
The actual command sequence is a two-step process. The ERASE SETUP (60h) com-
mand is first written to the command register. Then three cycles of addresses are written
to the device. Next, the ERASE CONFIRM (D0h) command is written to the command
register. At the rising edge of WE#, R/B# goes LOW and the control logic automatically
controls the timing and erase-verify operations. R/B# stays LOW for the entire
erase time.
The READ STATUS (70h) command can be used to check the status of the BLOCK ERASE
operation. When bit 6 = “1,” the ERASE operation is complete. Bit 0 indicates a pass/fail
condition where “0” = pass (see Figure 24, and Table 11 on page 26).
D0h
31
2Gb, 4Gb, 8Gb: x8, x16 NAND Flash Memory
t BERS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
70h
I/O 0 = 0 ERASE successful
I/O 0 = 1 ERASE error
Command Definitions
©2005 Micron Technology, Inc. All rights reserved.
Status
Don’t Care
t
BERS