is43lr32200b-6bl Integrated Silicon Solution, Inc., is43lr32200b-6bl Datasheet - Page 6

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is43lr32200b-6bl

Manufacturer Part Number
is43lr32200b-6bl
Description
512k X 32bits X 4banks Mobile Ddr Sdram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
Rev. 00A | Feb. 2011
Figure4 : Mode Register Set (MRS) Definition
Burst Type
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Table 3.
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
Note: M12(BA1) and M11(BA0) must be set to “0” to select Mode Register (vs. the Extended Mode Register)
12
BA1
0
11
BA0
0
A10
10
0
M6
0
0
0
0
1
1
1
1
M5
A9
0
0
1
1
0
0
1
1
9
0
M4
0
1
0
1
0
1
0
1
A8
8
0
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CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A7
7
0
2
3
A6
6
CAS Latency
- dram@issi.com
A5
5
M3
0
1
A4
4
Burst Type
Sequential
Interleave
A3
BT
3
A2
2
Burst Length
A1
1
M2
0
0
0
0
1
1
1
1
A0
0
M1
0
0
1
1
0
0
1
1
IS43/46LR32200B
M0
Address Bus
Mode Register (Mx)
Advanced Information
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
M3 = 0
16
2
4
8
Burst Length
Reserved
Reserved
Reserved
Reserved
M3 = 1
16
2
4
8
6

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