w25x10bl Winbond Electronics Corp America, w25x10bl Datasheet
w25x10bl
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... AND 4M-BIT 2.5V SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI W25X10BL/20BL/40BL Publication Release Date: October 14, 2009 - 1- Preliminary -- Revision A ...
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... Top/Bottom Block Protect (TB) ....................................................................................... 11 9.1.5 Reserved Bits ................................................................................................................. 11 9.1.6 Status Register Protect (SRP) ........................................................................................ 12 9.1.7 Status Register Memory Protection ................................................................................ 13 9.2 INSTRUCTIONS ........................................................................................................... 14 9.2.1 Manufacturer and Device Identification .......................................................................... 14 9.2.2 Instruction Set ................................................................................................................ 15 9.2.3 Write Enable (06h) ......................................................................................................... 16 9.2.4 Write Disable (04h) ........................................................................................................ 16 9.2.5 Read Status Register (05h) ............................................................................................ 18 9.2.6 Write Status Register (01h) ............................................................................................ 19 9.2.7 Read Data (03h) ............................................................................................................. 21 9.2.8 Fast Read (0Bh) ............................................................................................................. 22 W25X10BL/20BL/40BL - 2 - ...
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... SOIC 150-mil (Package Code SN) ...................................................................... 46 11.2 8-Pin SOIC 208-mil (Package Code SS) ...................................................................... 47 11.3 8-Pin PDIP 300-mil (Package Code DA) ...................................................................... 48 11.4 8-Contact 6x5mm WSON (Package Code ZP) ............................................................ 49 12. ORDERING INFORMATION ..................................................................................................... 51 12.1 Valid Part Numbers and Top Side Marking .................................................................. 52 13. REVISION HISTORY ................................................................................................................ 53 W25X10BL/20BL/40BL Publication Release Date: October 14, 2009 - 3 - Preliminary -- Revision A ...
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... Up to 256 bytes can be programmed at a time using the Page Program instruction. Pages can be erased in groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (block erase) or the entire chip (chip erase). The W25X10BL/20BL/40BL has 32/64/128 erasable sectors and 2/4/8 erasable 64KB blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage ...
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... PIN CONFIGURATION SOIC 150-MIL / 208-MIL Figure 1a. W25X10BL/20BL/40BL Pin Assignments, 8-pin SOIC 150 / 208-mil (Package Code SN & SS) 4. PAD CONFIGURATION WSON 6X5-MM Figure 1b. W25X10BL/20BL/40BL Pad Assignments, 8-pad WSON 6X5-mm (Package Code ZP) W25X10BL/20BL/40BL Publication Release Date: October 14, 2009 - 5 - Preliminary -- Revision A ...
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... PIN DESCRIPTION SOIC 150 / 208-MIL, PDIP 300-MIL, WSON 6X5-MM PIN NO. PIN NAME 1 / (IO1) 3 /WP 4 GND 5 DIO (IO0) 6 CLK 7 /HOLD 8 VCC W25X10BL/20BL/40BL I/O FUNCTION I Chip Select Input O Data Input / Output I Write Protect Input Ground I/O Data Input / Output I Serial Clock Input I Hold Input Power Supply - 6 - ...
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... Package Types W25X10BL/20BL/40BL are offered in an 8-pin plastic 150-mil width SOIC (package code SN) and 6x5- mm WSON (package code ZP), see figures 1a and 1b, respectively. The W25X40BL is offered in the 208-mil width SOIC (package code SS) and the 300-mil 8-pin PDIP (package code DA), see figure 1c. ...
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... High Voltage 010000h Generators 00FF00h 000000h Page Address Latch / Counter Beginning Page Address Data Byte Address Latch / Counter Figure 2. W25X10BL/20BL/40BL Block Diagram - 8 - 07FFFFh • Block 7 (64KB) • 0700FFh • • • 04FFFFh • Block 4 (64KB) • 0400FFh 03FFFFh • ...
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... Hold Function The /HOLD signal allows the W25X10BL/20BL/40BL operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus ...
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... Hardware write protection using Status Register and /WP pin. • Write Protection using Power-down instruction. Upon power- power-down the W25X10BL/20BL/40BL will maintain a reset condition while VCC is below the threshold value of V reset, all operations are disabled and no instructions are recognized. During power-up and after the ...
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... Status register bit location S6 is reserved for future use. Current devices will read 0 for this bit location recommended to mask out the reserved bit when testing the Status Register. Doing this will ensure compatibility with future devices. W25X10BL/20BL/40BL in AC characteristics). All, none or a portion of the memory W ...
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... When the SRP pin is set the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is high the Write Status Register instruction is allowed. W25X10BL/20BL/40BL Figure 3. Status Register Bit Locations - 12 - ...
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... W25X20BL (2M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 3 030000h - 03FFFFh 2 and 3 020000h - 03FFFFh 0 000000h - 00FFFFh 0 and 1 000000h - 01FFFFh 0 thru 3 000000h - 03FFFFh W25X10BL (1M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 1 010000h - 01FFFFh 0 000000h - 00FFFFh 0 and 1 000000h - 01FFFFh Publication Release Date: October 14, 2009 - 13 - DENSITY PORTION ...
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... INSTRUCTIONS The instruction set of the W25X10BL/20BL/40BL consists of nineteen basic instructions that are fully controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DIO input provides the instruction code. ...
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... Dual Output and Dual I/O data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 6. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 W25X10BL/20BL/40BL BYTE 2 BYTE 3 BYTE 4 (1) (S7–S0) S7– ...
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... Write Enable for Volatile Status Register instruction (Figure 5) will not set the Write Enable Latch (WEL) bit only valid for the Write Status Register instruction to change the volatile Status Register bit values. Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram W25X10BL/20BL/40BL Instruction (50h ...
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... DIO pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 6. Write Disable Instruction Sequence Diagram W25X10BL/20BL/40BL Publication Release Date: October 14, 2009 - 17 - Preliminary -- Revision A ...
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... Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 7. The instruction is completed by driving /CS high. Figure 7. Read Status Register Instruction Sequence Diagram W25X10BL/20BL/40BL - 18 - ...
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... Status Register bits will be refreshed to the new values within the time period of t Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period. Please refer to 9.1 for detailed Status Register Bit descriptions. Factory default for all status Register bits are 0. . W25X10BL/20BL/40BL Publication Release Date: October 14, 2009 - 19 - Preliminary -- Revision A (See AC ...
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... Figure 8. Write Status Register Instruction Sequence Diagram - 20 - W25X10BL/20BL/40BL ...
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... Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D. maximum of (see AC Electrical Characteristics Figure 9. Read Data Instruction Sequence Diagram W25X10BL/20BL/40BL Publication Release Date: October 14, 2009 - 21 - Preliminary -- Revision A ...
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... The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DIO pin is a “don’t care”. Figure 10. Fast Read Instruction Sequence Diagram W25X10BL/20BL/40BL (see AC Electrical Characteristics). This is accomplished by adding ...
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... DO and DIO, instead of just DO. This allows data to be transferred from the W25X10BL/20BL/40BL at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution ...
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... A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (See 9.2.13 for detail descriptions). Figure 12a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4 ≠ 10) W25X10BL/20BL/40BL - 24 - ...
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... Figure 12b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10) W25X10BL/20BL/40BL Publication Release Date: October 14, 2009 - 25 - Preliminary -- Revision A ...
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... Figure 13. Continuous Read Mode Reset for Fast Read Dual I/O Since W25X10BL/20BL/40BL does not have a hardware Reset pin the controller resets while W25X10BL/20BL/40BL are set to Continuous Mode Read, the W25X10BL/20BL/40BL will not recognize any initial standard SPI instructions from the controller. To address this possibility recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a system Reset ...
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... Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 14. Page Program Instruction Sequence Diagram W25X10BL/20BL/40BL Publication Release Date: October 14, 2009 - 27 - Preliminary -- Revision A ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 15. Sector Erase Instruction Sequence Diagram W25X10BL/20BL/40BL (See AC Characteristics). While the Sector Erase ...
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... Block Protect (SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 16. 32KB Block Erase Instruction Sequence Diagram W25X10BL/20BL/40BL 1 (See AC Characteristics). While the Block Erase BE Publication Release Date: October 14, 2009 ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 17. Block Erase Instruction Sequence Diagram W25X10BL/20BL/40BL (See AC Characteristics). While the Block Erase ...
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... Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 18. Chip Erase Instruction Sequence Diagram W25X10BL/20BL/40BL (See AC Characteristics). While the Chip Erase cycle Publication Release Date: October 14, 2009 ...
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... All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 19. Deep Power-down Instruction Sequence Diagram W25X10BL/20BL/40BL - 32 - ...
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... The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 20. The Device ID values for the W25X10BL/20BL/40BL are listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high ...
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... Figure 21. Release Power-down / Device ID Instruction Sequence Diagram - 34 - W25X10BL/20BL/40BL ...
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... Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 22. The Device ID values for the W25X10BL/20BL/40BL are listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... CLK with most significant bits (MSB) first as shown in figure 23. The Device ID values for the W25X10BL/20BL/40BL are listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25X10BL/20BL/40BL device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks ...
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... JEDEC ID (9Fh) For compatibility reasons, the W25X10BL/20BL/40BL provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The ...
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... Lead Temperature Electrostatic Discharge Voltage Notes: 1. Specification for W25X10BL/20BL/40BL are preliminary. See preliminary designation at the end of this document. 2. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability ...
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... Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. W25X10BL/20BL/40BL SYMBOL t (1) VSL t (1) PUW V (1) WI Figure 26. Power-up Timing and Voltage Levels - 40 - SPEC UNIT ...
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... IL Input High Voltage V IH Output Low Voltage V OL Output High Voltage V OH Notes: 1. Tested on sample basis and specified through design and characterization data. TA=25°C, VCC=3V. 2. Checker Board Pattern. W25X10BL/20BL/40BL MIN ( (2) OUT /CS = VCC, VIN = GND or VCC /CS = VCC, VIN = GND or VCC ...
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... AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. W25X10BL/20BL/40BL SYMBOL Figure 27. AC Measurement I/O Waveform ...
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... Not Active Setup Time relative to CLK /CS Deselect Time (for Array Read Array Read) /CS Deselect Time (for Erase or Program Read Status Registers and Volatile Status Register Write) Output Disable Time Clock Low to Output Valid Output Hold Time W25X10BL/20BL/40BL SYMBOL ALT MIN F f D.C. ...
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... Additional Byte Program Time (After First Byte) Page Program Time Sector Erase Time (4KB) Block Erase Time (32KB) Block Erase Time (64KB) Chip Erase Time W25X10BL / W25X20BL Chip Erase Time W25X40BL Notes: 1. Clock high + Clock low must be less than or equal to 1/f 2. ...
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... Serial Output Timing 10.9 Input Timing 10.10 Hold Timing W25X10BL/20BL/40BL Publication Release Date: October 14, 2009 - 45 - Preliminary -- Revision A ...
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... Controlling dimensions: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches W25X10BL/20BL/40BL MILLIMETERS Min Max 1 ...
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... Controlling dimensions: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches W25X10BL/20BL/40BL MILLIMETERS NOM MAX MIN 1 ...
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... PDIP 300-mil (Package Code DA) Symbol Min A --- A1 0.25 A2 3.18 B 0.41 B1 1. 7.37 E1 6.22 e1 2.29 L 3.05 α 8. --- W25X10BL/20BL/40BL Millimeters Typ. Max Min --- 4.45 --- --- --- 0.010 3.30 3.43 0.125 0.46 0.56 0.016 1.52 1.63 0.058 0.25 0.36 0.008 9.14 9.65 - 7.62 7.87 0.290 6.35 6.48 0.245 2.54 2.79 0.090 3.30 3.56 0.120 - 15 0 9.02 9.53 0.335 --- 1.14 --- - 48 - Inches Typ. Max --- 0.175 --- --- 0.130 0.135 0.018 0.022 0.060 0.064 ...
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... WSON (Package Code ZP) SYMBOL MIN A 0.70 A1 0. 5.90 D2 3.35 4. (2) L 0.55 y 0.00 W25X10BL/20BL/40BL MILLIMETERS TYP. MAX MIN 0.75 0.80 0.0275 0.02 0.05 0.0000 0.40 0.48 0.0137 0.20 REF 6.00 6.10 0.2322 3.40 3.45 0.1318 5.00 5.10 0.1929 4.30 4.35 0.1673 1.27 BSC 0.60 0.65 0.0216 - 0.75 0.0000 Publication Release Date: October 14, 2009 - 49 - INCHES TYP. MAX 0.0295 0.0314 0.0007 0.0019 ...
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... Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad. W25X10BL/20BL/40BL MILLIMETERS MIN TYP ...
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... T) or Tray (shape S), when placing orders. 1b. The “W” prefix is not included on the part marking Only the 2 letter is used for the part marking, package type ZP is not used for the part marking. W25X10BL/20BL/40BL (1) W 25X xxB 8-pad WSON 6x5mm DA = 8-pin PDIP 300mil ...
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... Valid Part Numbers and Top Side Marking The following table provides the valid part numbers for the W25X10BL/20BL/40BL SpiFlash Memories. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 12-digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 10-digit number ...
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... Information in this document is provided solely in connection with Winbond products. Winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice. W25X10BL/20BL/40BL All New create preliminary. Publication Release Date: October 14, 2009 ...