cy62137vll-70zxi Cypress Semiconductor Corporation., cy62137vll-70zxi Datasheet
cy62137vll-70zxi
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cy62137vll-70zxi Summary of contents
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... Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O LOW, then data from memory will appear on I/O the truth table at the back of this data sheet for a complete description of read and write modes ...
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... Product Portfolio V Range (V) CC [2] Product Min. Typ. CY62137VLL 2.7 3.0 [3] Pin Configurations Pin Definitions Pin Number Type 1–5, 18–22, 24–27, 42–45 Input 7–10, 13–16, 29–32, 35–38 Input/Output 23 No Connect 17 Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ 6 Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip 40, 39 Input/Control BHE, BLE ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC ...
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AC Test Loads and Waveforms OUTPUT OUTPUT INCLUDING JIG AND (a) SCOPE Equivalent to: Parameters Data Retention Characteristics Parameter Description V V for Data Retention ...
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... If both byte enables are toggled together this value is 10 ns. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. ...
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Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID [13, 14] Read Cycle No. 2 (OE Controlled) ADDRESS CE t ACE LZOE LZOE BHE/BLE t DBE t LZBE HIGH IMPEDANCE DATA ...
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Switching Waveforms (continued) [10, 15, 16] Write Cycle No. 1 (WE Controlled) ADDRESS BHE/BLE OE 17 DATA I/O NOTE t HZOE [10, 15, 16] Write Cycle No. 2 (CE Controlled) ADDRESS CE WE BHE/BLE OE DATA ...
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Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS CE BHE/BLE NOTE 17 DATA I/O t HZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) ADDRESS CE BHE/BLE NOTE 17 DATA ...
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Typical DC and AC Characteristics Normalized Operating Current vs. Supply Voltage 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.7 2.2 SUPPLY VOLTAGE (V) Access Time vs. Supply Voltage 1.0 1.9 SUPPLY ...
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... Ordering Information Speed Ordering Code (ns) 55 CY62137VLL-55ZI CY62137VLL-55ZXI 70 CY62137VLL-70ZI CY62137VLL-70ZXI CY62137VLL-70ZE CY62137VLL-70ZXE CY62137VLL-70ZSXE Please contact your local Cypress sales representative for availability of these parts Package Diagrams 22 23 TOP VIEW 0.400(0.016) 0.800 BSC 0.300 (0.012) (0.0315) 18.517 (0.729) 18.313 (0.721) MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders ...
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Document History Page ® Document Title: CY62137V MoBL 2M (128K x 16) Static RAM Document Number: 38-05051 Orig. of REV. ECN NO. Issue Date Change ** 109960 10/03/01 SZV *A 116788 09/04/02 GBI *B 237428 See ECN AJU *C 329640 ...