cy62167e Cypress Semiconductor Corporation., cy62167e Datasheet
cy62167e
Manufacturer Part Number
cy62167e
Description
16-mbit 1m X 16 / 2m X 8 Static Ram
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
1.CY62167E.pdf
(12 pages)
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Cypress Semiconductor Corporation
Document #: 001-15607 Rev. *A
Features
Functional Description
The CY62167E is a high performance CMOS static RAM
organized as 1M words by 16 bits/2M words by 8 bits. This
device features advanced circuit design to provide an ultra low
active current. This is ideal for providing More Battery Life™
(MoBL
The device also has an automatic power down feature that
reduces power consumption by 99% when addresses are not
toggling. Place the device into standby mode when deselected
Logic Block Diagram
Note
1. For best practice recommendations, refer to the Cypress application note
• Configurable as 1M x 16 or as 2M x 8 SRAM
• Very high speed: 45 ns
• Wide voltage range: 4.5V–5.5V
• Ultra low standby power
• Ultra low active power
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in 48-pin TSOP I package
— Typical standby current: 1.5 µA
— Maximum standby current: 12 µA
— Typical active current: 2.2 mA @ f = 1 MHz
POWER DOWN
®
) in portable applications such as cellular telephones.
CIRCUIT
[1]
A
A
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
1
0
1
, CE
CE
CE
BHE
BLE
2
, and OE features
2
1
•
198 Champion Court
COLUMN DECODER
16-Mbit (1M x 16 / 2M x 8) Static RAM
DATA IN DRIVERS
1M × 16 / 2M x 8
RAM ARRAY
AN1064, SRAM System
(CE
The input and output pins (IO
high impedance state when:
To write to the device, take Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO
written into the location specified on the address pins (A
through A
from the IO pins (IO
specified on the address pins (A
To read from the device, take Chip Enables (CE
CE
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appears on IO
then data from memory appears on IO
Table” on page 10
modes.
• The device is deselected (CE
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
• A write operation is in progress (CE
(BHE, BLE HIGH) or
WE LOW)
2
1
HIGH) and Output Enable (OE) LOW while forcing the
HIGH, or CE
•
19
San Jose
). If Byte High Enable (BHE) is LOW, then data
Guidelines.
for a complete description of read and write
2
0
8
,
to IO
LOW, or both BHE and BLE are HIGH).
through IO
CA 95134-1709
7
. If Byte High Enable (BHE) is LOW,
0
CY62167E MoBL
through IO
0
15
1
HIGH or CE
through A
) is written into the location
IO
IO
OE
BLE
BYTE
BHE
WE
8
1
Revised June 07, 2007
0
8
to IO
–IO
–IO
LOW, CE
•
15
7
15
0
19
15
) are placed in a
1
through IO
).
. See the
2
LOW and CE
408-943-2600
LOW)
2
1
HIGH, and
LOW and
CE
CE
2
1
“Truth
7
), is
®
2
0
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