m36w832te STMicroelectronics, m36w832te Datasheet - Page 25

• Manufacturer Part Number: m36w832te
• Description: 32 Mbit 2mb X16, Boot Block Flash Memory And 8 Mbit 512kb X16 Sram, Multiple Memory Product
• Manufacturer: STMicroelectronics

SRAM Operations
There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Read. Read operations are used to output the
contents of the SRAM Array.
The SRAM is in Byte Read mode whenever Write
Enable, WS, is at V
Chip Enable, E1S, is at V
at V
The SRAM is in Word Read mode whenever Write
Enable, WS, is at V
Byte Enable inputs UBS and LBS are both at V
and the two Chip Enable inputs, E1S, and E2S are
Don’t Care.
Valid data will be available on the output pins after
a time of t
Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t
er than the address. Data out may be indetermi-
nate at t
will always be valid at t
14 and 15).
Write. Write operations are used to write data to
the SRAM. The SRAM is in Write mode whenever
WS and E1S are at V
the Chip Enable inputs, E1S and E2S, or the Write
Enable input, WS, must be deasserted during ad-
dress transitions for subsequent write cycles.
IH
, and UBS or LBS is at V
E1LQX
AVQV
, t
after the last stable address. If the
E2HQX
IH
IH
E1LQV
, Output Enable, GS, is at V
, Output Enable, GS, is at V
IL
AVQV
, and E2S is at V
and t
IL
, t
, Chip Enable, E2S, is
(see Table 20, Figures
E2HQV
GLQX
IL
.
, or t
, but data lines
GLQV
IH
. Either
) rath-
IL
IL
IL
,
,
A Write operation is initiated when E1S is at V
E2S is at V
o the falling edge of E1S, the rising edge of E2S or
the falling edge of WS, whichever occurs last. The
Write cycle is terminated on the rising edge of
E1S, the rising edge of WS or the falling edge of
E2S, whichever occurs first.
If the Output is enabled (E1S=V
GS=V
impedance within t
must be taken to avoid bus contention in this type
of operation. The Data input must be valid for t
VWH
t
before the falling edge of E2S, whichever occurs
first, and remain valid for t
(see Table 21, Figure 17, 18, 19 and 20).
Standby/Power-Down. The SRAM component
has a chip enabled power-down feature which in-
vokes an automatic standby mode (see Table 20
and Figure 16). The SRAM is in Standby mode
whenever either Chip Enable is deasserted, E1S
at V
Data Retention. The SRAM data retention per-
formance as V
scribed in Table 22, Figures 21 and 22, SRAM
Low V
Controlled and SRAM Low V
AC Waveforms, E2S Controlled, respectively.
Output Disable. The data outputs are high im-
pedance when the Output Enable, GS, is at V
with Write Enable, WS, at V
DVE1H
IH
before the rising edge of Write Enable, for
IL
or E2S at V
DDS
before the rising edge of E1S or for t
), then WS will return the outputs to high
IH
Data Retention AC Waveforms, E1S
and WS is at V
DDS
IL
M36W832TE, M36W832BE
WLQZ
.
goes down to V
of its falling edge. Care
WHDX
IH
IL
. The data is latched
.
DDS
, t
IL
E1HAX
Data Retention
, E2S=V
DR
or t
are de-
IH
DVE2L
E2LAX
25/64
and
IL
D-
IH
,