m48z128 STMicroelectronics, m48z128 Datasheet - Page 9

• Manufacturer Part Number: m48z128
• Description: 5.0v Or 3.3v, 1 Mbit 128 Kbit X 8 Zeropower Sram
• Manufacturer: STMicroelectronics

WRITE Mode
The M48Z128/Y/V is in the WRITE Mode whenev-
er W and E are active. The start of a WRITE is ref-
erenced from the latter occurring falling edge of W
or E. A WRITE is terminated by the earlier rising
edge of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for minimum of
t
Figure 8. WRITE Enable Controlled, WRITE AC Waveforms
Note: Output Enable (G) = High.
Figure 9. Chip Enable Controlled, WRITE AC Waveforms
Note: Output Enable (G) = High.
EHAX
from E or t
A0-A16
E
W
DQ0-DQ7
A0-A16
E
W
DQ0-DQ7
WHAX
from W prior to the initiation
tAVEL
tAVEL
tAVWL
tAVWL
tWLQZ
tAVWH
tAVEH
tWLWH
tAVAV
VALID
tAVAV
VALID
tELEH
of another READ or WRITE cycle. Data-in must be
valid t
valid for t
kept high during WRITE cycles to avoid bus con-
tention; although, if the output bus has been acti-
vated by a low on E and G, a low on W will disable
the outputs t
tDVEH
DVWH
tDVWH
DATA INPUT
WHDX
M48Z128, M48Z128Y, M48Z128V*
DATA INPUT
tWHDX
prior to the end of WRITE and remain
WLQZ
or t
after W falls.
EHDX
tEHDX
tWHQX
afterward. G should be
tEHAX
tWHAX
AI01198
AI01199
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