m48z18 STMicroelectronics, m48z18 Datasheet - Page 6

• Manufacturer Part Number: m48z18
• Description: 5v, 64 Kbit 8kb X 8 Zeropower Sram
• Manufacturer: STMicroelectronics

M48Z08, M48Z18
WRITE Mode
The M48Z08/18 is in the WRITE Mode whenever
W and E are active. The start of a WRITE is refer-
enced from the latter occurring falling edge of W or
E.
A WRITE is terminated by the earlier rising edge of
W or E. The addresses must be held valid through-
out the cycle. E or W must return high for a mini-
mum of t
Figure 6. WRITE Enable Controlled, WRITE Mode AC Waveform
Figure 7. Chip Enable Controlled, WRITE Mode AC Waveforms
6/16
EHAX
A0-A12
E
W
DQ0-DQ7
A0-A12
E
W
DQ0-DQ7
from Chip Enable or t
tAVEL
tAVEL
tAVWL
tAVWL
WHAX
tWLQZ
from
tAVWH
tAVEH
tWLWH
tAVAV
VALID
tAVAV
VALID
tELEH
WRITE Enable prior to the initiation of another
READ or WRITE cycle. Data-in must be valid t
VWH
t
WRITE cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
after W falls.
WHDX
prior to the end of WRITE and remain valid for
tDVEH
tDVWH
afterward. G should be kept high during
DATA INPUT
DATA INPUT
tWHDX
tEHDX
tWHQX
tEHAX
tWHAX
AI01387B
AI01386
WLQZ
D-