psd813f3 STMicroelectronics, psd813f3 Datasheet
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psd813f3 Summary of contents
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... FEATURES SUMMARY FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERAL FOR 8-BIT MCUS DUAL BANK FLASH MEMORIES – Mbit OF PRIMARY FLASH MEMORY (8 Uniform Sectors, 32K x8) – 256 Kbit SECONDARY FLASH MEMORY (4 Uniform Sectors) – Concurrent operation: READ from one memory while erasing and writing the ...
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... Memory Block Select Signals INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Primary Flash Identifier Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Reading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data Polling Flag (DQ7 Toggle Flag (DQ6 Error Flag (DQ5 Erase Time-out Flag (DQ3 PROGRAMMING FLASH MEMORY Data Polling ...
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... Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Flash Memory Sector Protect Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Reset (RESET) Signal (on the PSD83xF2 and PSD85xF2 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SECTOR SELECT AND SRAM SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . . 30 Configuration Modes for MCUs with Separate Program and Data Spaces ...
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... I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Reset of Flash Memory Erase and Program Cycles (on the PSD834Fx PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 69 Standard JTAG Signals JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Security and Flash memory Protection INITIAL DELIVERY STATE AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 MAXIMUM RATING AND AC PARAMETERS PACKAGE MECHANICAL ...
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PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Using ST’s special Fast-JTAG programming, a de- sign can be rapidly programmed into the PSD in as little as seven seconds. Table 1. Product Range Primary Flash (1) Memory Part Number (8 Sectors) PSD813F2 1 Mbit PSD813F3 1 Mbit PSD813F4 1 Mbit PSD813F5 1 Mbit PSD833F2 1 Mbit PSD834F2 2 Mbit PSD853F2 1 Mbit ...
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Figure 2. PQFP52 Connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 GND 9 PC3 10 PC2 11 PC1 12 PC0 13 PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 39 AD15 38 AD14 ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 3. PLCC52 Connections 8 PD2 9 PD1 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 GND 17 PC3 18 PC2 19 PC1 20 PC0 8/110 AD15 46 AD14 ...
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Figure 4. TQFP64 Connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 GND 10 GND 11 PC3 12 PC2 13 PC1 14 PC0 PSD813F2, ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PIN DESCRIPTION Table 2. Pin Description (for the PLCC52 package - Note 1) Pin Name Pin Type This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: ...
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Pin Name Pin Type Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low Reset Power-up. These pins make up Port A. These port pins are configurable and can have the following functions: ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Pin Name Pin Type PC2 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD ...
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... MCU I/O - write to or read from a standard output or input port. Input to the PLDs. PD2 8 I/O CPLD output (External Chip Select). PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O. When High, the PSD memory blocks are disabled to conserve power. V 15, 38 Supply Voltage CC ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 5. PSD Block Diagram 14/110 AI02861E ...
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... Blocks, page 19. The 1 Mbit or 2 Mbit (128K 256K x 8) Flash memory is the primary memory of the PSD di- vided into 8 equally-sized sectors that are individ- ually selectable. The optional 256 Kbit (32K x 8) secondary Flash memory is divided into 4 equally-sized sectors ...
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... SRAM. The secondary memory can be programmed the same way by ex- ecuting out of the primary Flash memory. The PLD or other PSD Configuration blocks can be pro- grammed through the JTAG port or a device pro- grammer ...
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... The designer does not need to enter Hardware Description Lan- guage (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 6. PS- Dsoft Express is available from our web site (the address is given on the back page of this data sheet) or other distribution channels ...
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... Read only – PSD Security and Secondary Flash C2 memory Sector Protection C7 Enables JTAG Port B0 Power Management Register 0 B4 Power Management Register 2 E0 Page Register Places PSD memory areas in Program and/or E2 Data space on an individual basis. Port B Port B (3:0) Port B (7:4) Address a11-a8 N/A Address a11-a8 Address a15-a12 Address a3-a0 ...
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... The PSD has the following memory blocks: – Primary Flash memory – Optional Secondary Flash memory – Optional SRAM The Memory Select signals for these blocks origi- nate from the Decode PLD (DPLD) and are user- defined in PSDsoft Express. Secondary Flash Memory Sector Size Sector Select Signal ...
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... However, Flash memory can only be altered using specific Erase and Program instructions. For example, the MCU cannot write a single byte di- rectly to Flash memory as it would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a Program instruction, then (CSBOOT0- test the status of the Program cycle ...
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... The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. 11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase mode ...
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... Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sector whose protection has to be verified. The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. (CSBOOT0- The sector protection status for all NVM blocks ...
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... DQ7-DQ0 represent the Data Bus bits, D7-D0. 3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See the section entitled PROGRAMMING FLASH MEMORY, page 25 details ...
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... The Error Flag Bit (DQ5) may also indicate a Time-out condition while attempting to program a byte. In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash memory sector in which the error occurred or to which the pro- grammed byte belongs must no longer be used ...
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... PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 ming algorithm has completed, to compare the byte that was written to the Flash memory with the byte that was intended to be written. When using the Data Polling method during an Erase cycle, Figure Data Polling Flag Bit (DQ7) is '0' until the Erase cy- cle is complete ...
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... It is suggested (as with all Flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the byte that was written to Flash memory with the byte that was intended to be written. When using the Data Toggle method after an ...
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... Flash memory sector with 00h as the PSD does this automatically before erasing (byte = FFh). During a Sector Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in the section entitled ...
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... Sec7_Prot Sec6_Prot Sec5_Prot Note: 1. Bit Definitions: Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write protected. Sec<i>_Prot 0 = Primary Flash memory or secondary Flash memory Sector <i> is not write protected. Table 12. Sector Protection/Security Bit Definition – PSD/EE Protection Register Bit 7 Bit 6 Bit 5 ...
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... SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to Voltage Stand- PC2). If you have an ...
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... Flash memory segment 0. Any address greater than 9FFFh ac- cesses the primary Flash memory segment 0. You can see that half of the primary Flash memory seg- ment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Also note that an equation that defined FS1 to any- where in the range of 8000h to BFFFh would not be valid ...
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... Figure 10. 8031 Memory Modules – Separate Space DPLD RS0 CSBOOT0-3 FS0-FS7 PSEN RD Figure 11. 8031 Memory Modules – Combined Space DPLD RD VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 VM REG BIT 0 Table 13. VM Register Bit 7 Bit 6 Bit 5 ...
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... Figure 12. Page Register RESET 32/110 If memory paging is not needed not all 8 page register bits are needed for memory paging, then these bits may be used in the CPLD for general logic. See Application Note AN1154. Figure 12 shows the Page Register. The eight flip- ...
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... PLDs. The DPLD performs address decoding for Select signals for internal components, such as memory, registers, and I/O ports. The CPLD can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic. These ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 13. PLD Diagram 34/110 PORTS I/O BUS INPUT PLD ...
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... The DPLD can be used to generate the following decode signals: 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) Figure 14. DPLD Logic Array (INPUTS PORTS (PORT A,B,C) MCELLAB.FB [7:0] (FEEDBACKS) MCELLBC ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be ...
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Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are con- nected to Ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and are named as McellBC0-McellBC7. ...
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... This is called product term expansion. PSDsoft Express performs this expansion as needed. Loading and Reading the Output Macrocells (OMC) The Output Macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP block (see the section enti- tled I/O PORTS, page 51). The flip-flops in each of the 16 Output Macrocells (OMC) can be loaded from the data bus by a MCU ...
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Figure 16. CPLD Output Macrocell PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 ARRAY AND BUS INPUT PLD 39/110 ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Input Macrocells (IMC) The CPLD has 24 Input Macrocells (IMC), one for each pin on Ports A, B, and C. The architecture of the Input Macrocells (IMC) is shown in 17., page 41. The Input ...
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Figure 17. Input Macrocell PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 ARRAY AND BUS INPUT PLD 41/110 ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 18. Handshaking Communication Using Input Macrocells 42/110 ...
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MCU BUS INTERFACE The “no-glue logic” MCU Bus Interface block can be directly connected to most popular MCUs and their control signals. Key 8-bit MCUs, with their Table 16. MCUs and their Control Signals Data Bus MCU CNTL0 Width 8031 ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PSD Interface to a Multiplexed 8-Bit Bus Figure 19 shows an example of a system using a MCU with an 8-bit multiplexed bus and a PSD. The ADIO port on the PSD is connected directly ...
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PSD Interface to a Non-Multiplexed 8-Bit Bus Figure 20 shows an example of a system using a MCU with an 8-bit non-multiplexed bus and a PSD. The address bus is connected to the ADIO Port, and the data bus is ...
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... T1 1 P1.0 2 P1.1 3 P1.2 4 P1.3 5 P1.4 6 P1.5 7 P1.6 PSEN 8 P1.7 ALE/P RESET 46/110 CNTL1), and Write Strobe (WR, CNTL0) may be used for accessing the internal memory and I/O Ports blocks. Address Strobe (ALE/AS, PD0) latches the address. AD0 39 AD0 AD1 P0.0 38 AD1 AD2 P0.1 37 AD3 AD2 P0.2 36 AD3 AD4 P0.3 AD5 35 AD4 P0 ...
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The Intel 80C251 MCU features a user-config- urable bus interface with four possible bus config- urations, as shown in Table 18., page The first configuration is 80C31-compatible, and the bus interface to the PSD is identical to that shown ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 23. Interfacing the PSD with the 80C251, with RD and PSEN Inputs 80C251SB 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 ...
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The Philips 80C51XA MCU family supports 16-bit multiplexed bus that can have burst cy- cles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4) ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 68HC11 Figure 25 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit multiplexed mode with E and R/W settings. The DPLD can be Figure 25. Interfacing the PSD with a ...
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I/O PORTS There are four programmable I/O ports: Ports and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 26. General I/O Port Architecture DATA OUT REG ADDRESS D Q ALE G MACROCELL OUTPUTS EXT CS READ MUX CONTROL REG DIR REG ...
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... Port B in Address Out Mode. Note: Do not drive address signals with Address Out Mode to an external memory device in- tended for the MCU to Boot from the external de- vice. The MCU must first Boot from PSD memory so the Direction and Control register bits can be set ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 20. Port Operating Mode Settings Defined in Mode PSDabel MCU I/O Declare pins only PLD I/O Logic equations Data Port (Port A) N/A Address Out Declare pins only (Port A,B) Address In Logic for ...
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... Port and D. The address input can be latched in the Input Macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is included in the DPLD equations for the SRAM, or primary or secondary Flash memory is considered address input. Data Port Mode Port A can be used as a data bus port for a MCU with a non-multiplexed address/data bus ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 JTAG In-System Programming (ISP) Port C is JTAG compliant, and can be used for In- System Programming (ISP). You can multiplex JTAG operations with other functions on Port C because In-System Programming (ISP) is not ...
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Table 26. Drive Register Pin Assignment Drive Bit 7 Bit 6 Register Open Open Port A Drain Drain Open Open Port B Drain Drain Open Open Port C Drain Drain 1 1 Port Note ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Input Macrocells (IMC) The Input Macrocells (IMC) can be used to latch or store external inputs. The outputs of the Input Macrocells (IMC) are routed to the PLD input bus, and can be read by ...
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Port C – Functionality and Structure Port C can be configured to perform one or more of the following functions (see Figure 29): MCU I/O Mode CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or Port C. ...
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... Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions: Address Strobe (ALE/AS, PD0) CLKIN (PD1) as input to the macrocells flip- flops and APD counter PSD Chip Select Input (CSI, PD2). Driving this signal High disables the Flash memory, SRAM and CSIOP. REG. DATA OUT D Q ...
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External Chip Select The CPLD also provides three External Chip Se- lect (ECS0-ECS2) outputs on Port D pins that can be used to select external devices. Each External Chip Select (ECS0-ECS2) consists of one product Figure 31. Port D External ...
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... POWER MANAGEMENT All PSD devices offer configurable power saving options. These options may be used individually or in combinations, as follows: All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design ...
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... Operating mode if either PSD Chip Select Input (CSI, PD2) is Low or the Reset (RESET) input is High. – The MCU address/data bus is blocked from all memory and PLDs. – Various signals can be blocked (prior to Power-down mode) from entering the PLDs by setting the appropriate bits in the PMMR Figure 32 ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 For Users of the HC11 (or compatible) The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11 (or compati- ble) in your design, and you wish to use ...
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Table 30. Power Management Mode Registers PMMR0 (Note 1) Bit Not used, and should be set to zero off Automatic Power-down (APD) is disabled. Bit 1 APD Enable Automatic Power-down (APD) is ...
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... EEPROM, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A High on PSD Chip Select Input (CSI, PD2) dis- ables the Flash memory, EEPROM, and SRAM, and reduces the PSD power consumption. How- ever, the PLD and I/O signals remain operational when PSD Chip Select Input (CSI, PD2) is High ...
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... A Reset (RESET) also resets the internal Flash . LKO memory state machine. During a Flash memory Program or Erase cycle, Reset (RESET) termi- nates the cycle and returns the Flash memory to the Read Mode within a period OPR period is needed before the device 34 shows ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode Port Configuration Power-On Reset MCU I/O Input mode Valid after internal PSD PLD Output configuration bits are loaded Address Out Tri-stated Data Port Tri-stated ...
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... PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE The JTAG Serial Interface block can be enabled on Port C (see Table 34., page blocks (primary and secondary Flash memory), PLD logic, and PSD Configuration Register bits may be programmed through the JTAG Serial In- terface block. A blank device can be mounted on a printed circuit board and programmed using JTAG ...
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... JTAG channel. See Application Note AN1153. TERR indicates if an error has occurred when erasing a sector or programming a byte in Flash memory. This signal goes Low (active) when an Error condition occurs, and stays Low until an “ISC_CLEAR” command is executed or a chip Re- set ...
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... INITIAL DELIVERY STATE When delivered from ST, the PSD device has all bits in the memory and PLDs set to ’1.’ The PSD Configuration Register bits are set to ’0.’ The code, configuration, and PLD logic are loaded using the Table 35. JTAG Enable Register 0 = off JTAG port is disabled ...
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... PSD is in each mode. Also, the supply power is considerably different if the Turbo Bit is ’0.’ – The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figures mA/MHz as a function of the number of Product Terms (PT) used. – ...
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... Power-down Mode Number of product terms used (from fitter report total product terms Turbo Mode I total CC This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based 0mA. OUT PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 = 5.0V (Turbo Mode On) CC Conditions ...
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... Operational Modes % Normal % Power-down Mode Number of product terms used (from fitter report total product terms Turbo Mode I total CC This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based 0mA. OUT 74/110 = 5.0V (Turbo Mode Off) CC Conditions = 8 MHz = 4 MHz ...
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... Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 1 or Hi-Z) ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are ...
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Table 44. Capacitance Symbol Parameter C Input Capacitance (for input pins) IN Output Capacitance (for input/ C OUT output pins) C Capacitance (for CNTL2/V VPP Note: 1. Sampled only, not 100% tested. 2. Typical values are for T = 25°C ...
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... Supply 5 (Note ) Current Flash memory SRAM PLD AC Adder I (AC) CC Flash memory AC Adder 5 (Note ) SRAM AC Adder Note: 1. Reset (RESET) has hysteresis. V IL1 2. CSI deselected or internal Power-down mode is active. 3. PLD is in non-Turbo mode, and none of the inputs are switching. 4. Please see Figure 35., page 72 for the PLD current calculation ...
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... Supply 5 (Note ) Current Flash memory SRAM PLD AC Adder I (AC) CC Flash memory AC Adder 5 (Note ) SRAM AC Adder Note: 1. Reset (RESET) has hysteresis. V IL1 2. CSI deselected or internal PD is active. 3. PLD is in non-Turbo mode, and none of the inputs are switching. 4. Please see Figure 36., page 72 for the PLD current calculation. ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 40. Input to Output Disable / Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE Table 47. CPLD Combinatorial Timing (5V devices) Symbol Parameter Conditions CPLD Input Pin/ t Feedback to CPLD PD Combinatorial Output CPLD Input ...
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Figure 41. Synchronous Clock Mode Timing – PLD CLKIN INPUT REGISTERED OUTPUT Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices) Symbol Parameter Conditions Maximum Frequency 1/( External Feedback Maximum Frequency f MAX Internal 1/( ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices) Symbol Parameter Conditions Maximum Frequency 1/(t External Feedback Maximum Frequency f 1/(t MAX Internal Feedback (f ) CNT Maximum 1/(t Frequency Pipelined Data t Input ...
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Figure 42. Asynchronous Reset / Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 43. Asynchronous Clock Mode Timing (product term clock) CLOCK INPUT REGISTERED OUTPUT PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 tARPW tARP tCHA tCLA tSA tHA tCOA AI02864 AI02859 83/110 ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices) Symbol Parameter Conditions Maximum Frequency 1/( External Feedback Maximum Frequency f Internal 1/(t +t MAXA SA COA Feedback (f ) CNTA Maximum Frequency ...
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Table 52. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices) Symbol Parameter Conditions Maximum Frequency 1/(t SA External Feedback Maximum Frequency f MAXA Internal 1/( Feedback (f ) CNTA Maximum 1/(t Frequency CHA Pipelined Data Input Setup t ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 44. Input Macrocell Timing (product term clock) PT CLOCK INPUT OUTPUT AI03101 Table 53. Input Macrocell Timing (5V devices) Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input ...
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Figure 45. READ Timing t AVLX ALE /AS t LVLX A /D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS AVPV Note and t are not required for 80C251 ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 55. READ Timing (5V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid ...
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Table 56. READ Timing (3V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV RD ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 46. WRITE Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS 90/110 t AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL ...
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... WR has the same timing as E, LDS, UDS, WRL, and WRH signals. 4. Assuming data is stable before active WRITE signal. 5. Assuming WRITE is active before data becomes valid. 6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 -70 ...
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... Assuming data is stable before active WRITE signal. 5. Assuming WRITE is active before data becomes valid. 6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. Table 59. Program, WRITE and Erase Times (5V devices) Symbol ...
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Table 60. Program, WRITE and Erase Times (3V devices) Symbol Flash Program 1 Flash Bulk Erase (pre-programmed) Flash Bulk Erase (not pre-programmed) t Sector Erase (pre-programmed) WHQV3 t Sector Erase (not pre-programmed) WHQV2 t Byte Program WHQV1 Program / Erase ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 47. Peripheral I/O READ Timing ALE/AS A/D BUS CSI RD Table 61. Port A Peripheral Data Mode READ Timing (5V devices) Symbol Parameter Address Valid to Data t AVQV–PA Valid t CSI Valid to ...
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Table 62. Port A Peripheral Data Mode READ Timing (3V devices) Symbol Parameter t Address Valid to Data Valid AVQV–PA t CSI Valid to Data Valid SLQV– Data Valid t RLQV– Data Valid 8031 Mode t ...
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... Warm Reset (on the PSD834Fx) NLNH–A t RESET High to Operational Device OPR Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode. 96/110 -12 Conditions Min Max Min Max Min Max 2 ...
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Table 67. V Timing (5V devices) STBYON Symbol Parameter t V Detection to V BVBH STBY STBYON V Off Detection to V STBY t BXBL Low Note timing is measured at V STBYON CC Table 68. V Timing ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 50. ISC Timing t ISCCH TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO Table 69. ISC Timing (5V devices) Symbol Parameter Clock (TCK, PC1) Frequency (except for t ISCCF PLD) Clock (TCK, PC1) High Time (except ...
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Table 70. ISC Timing (3V devices) Symbol Parameter Clock (TCK, PC1) Frequency (except for t ISCCF PLD) Clock (TCK, PC1) High Time (except for t ISCCH PLD) Clock (TCK, PC1) Low Time (except for t ISCCL PLD) t Clock (TCK, ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 PACKAGE MECHANICAL Figure 51. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing QFP-A Note: Drawing is not to scale. 100/110 ...
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Table 73. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions Symb. Typ 2. 13.20 D1 10.00 D2 7.80 E 13.20 E1 10.00 E2 7.80 e 0.65 L 0. ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Figure 52. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing PLCC-B Note: Drawing is not to scale. Table 74. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical ...
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Figure 53. TQFP64 - 64-lead Thin Quad Flatpack, Package Outline QFP-A Note: Drawing is not to scale. PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 Table 75. TQFP64 - 64-lead Thin Quad Flatpack, Package Mechanical Data Symb. Typ 0.10 A2 1.40 3.5° 16.00 D1 14.00 D2 12.00 E 16.00 E1 14.00 E2 12.00 e ...
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... Kbit Flash Memory Capacity Mbit (128K Mbit (256K x 8) 2nd Flash Memory 2 = 256 Kbit Flash memory + SRAM 3 = SRAM but no Flash memory 4 = 256 Kbit Flash memory but no SRAM Flash memory + no SRAM Operating Voltage blank = V = 4 3.0 to 3.6V ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 APPENDIX A. PQFP52 PIN ASSIGNMENTS Table 77. PQFP52 Connections (Figure 2) Pin Number Pin Assignments ...
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APPENDIX B. PLCC52 PIN ASSIGNMENTS Table 78. PLCC52 Connections (Figure 3) Pin Number Pin Assignments PC2 ( ...
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 APPENDIX C. TQFP64 PIN ASSIGNMENTS Table 79. TQFP64 Connections (Figure 4) Pin Number Pin Assignments ...
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REVISION HISTORY Table 80. Document Revision History Date Rev. 15-Oct-99 1.0 Initial release as a WSI document 27-Oct-00 1.1 Port A Peripheral Data Mode Read Timing, changed to 50 30-Nov-00 1.2 PSD85xF2 added 23-Oct-01 2.0 Document rewritten using the ST ...
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... No license implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are s to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products a authorized for use as critical components in life support devices or systems without express written approval of STMicroelectron The ST logo is a registered trademark of STMicroelectronics ...