74LVQ273QSCX Fairchild Semiconductor, 74LVQ273QSCX Datasheet
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74LVQ273QSCX
Specifications of 74LVQ273QSCX
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74LVQ273QSCX Summary of contents
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... Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC © 2001 Fairchild Semiconductor Corporation Features Ideal for low power/low noise 3.3V applications Implements patented EMI reduction circuitry ...
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Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...
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AC Electrical Characteristics Symbol Parameter f Maximum Clock MAX Frequency t Propagation Delay PLH Propagation Delay PHL Propagation Delay PHL Output to Output OSHL t ...
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Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide www.fairchildsemi.com Package Number M20B 4 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...