lh28f160s5h-l Sharp Microelectronics of the Americas, lh28f160s5h-l Datasheet
lh28f160s5h-l
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lh28f160s5h-l Summary of contents
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... Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 16 M-bit ( 8 16) Smart 5 Flash Memories (Fast Programming) • High performance read access time LH28F160S5-L70 – (5.0±0.25 V)/80 ns (5.0±0.5 V) LH28F160S5H-L70 – (5.0±0.25 V)/90 ns (5.0±0.5 V) LH28F160S5-L10/S5H-L10 – 100 ns (5.0±0.5 V) • Enhanced automated suspend options – Write suspend to read suspend – ...
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... COMPARISON TABLE OPERATING VERSIONS TEMPERATURE LH28F160S5-L70/L10 0 to +70˚C LH28F160S5H-L70/L10 – +85˚C PIN CONNECTIONS 56-PIN TSOP (Type RP ...
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PIN CONNECTIONS (contd.) 64-BALL CSP ...
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BLOCK DIAGRAM OUTPUT BUFFER Y INPUT A -A DECODER 0 20 BUFFER ADDRESS X LATCH DECODER ADDRESS COUNTER DQ - INPUT BUFFER QUERY ROM IDENTIFIER REGISTER STATUS REGISTER MULTIPLEXER DATA COMPARATOR Y GATING WRITE STATE 32 64 k-BYTE ...
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... DATA INPUT/OUTPUTS : DQ -DQ 0 memory array, status register, query, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally INPUT/ DQ -DQ latched during a write cycle OUTPUT DQ -DQ 8 array read cycles in x16 mode; not used for status register, query and identifier code read mode ...
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... A word/byte write is performed in byte increments typically within 9.24 µ word/byte write has high speed write performance of 2 µs/byte ( write suspend mode enables the system to read data from, or write data to any other flash memory and CC array location. PP Individual block locking uses a combination of bits and WP#, thirty-two block lock-bits, to lock and unlock blocks ...
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... The access time the V AVQV voltage range of 4.75 to 5.25 V over the temperature range +70°C (LH28F160S5-L)/ – +85°C (LH28F160S5H-L). At 4 time is 80 ns/100 ns (LH28F160S5-L70/S5-L10 ns/100 ns (LH28F160S5H-L70/S5H-L10). The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching) ...
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... Write suspend allows system software to suspend a (multi) word/byte write to read data from any other flash memory array location. 2.1 Data Protection Depending on the application, the system designer ...
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... BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, query structure, or independent of the V voltage. RP# must ...
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... Lock locked. The Clear Block Lock- Block 31 Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first) ...
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... Read Identifier 9 V Codes Query 9 V Write NOTES : " 1. Refer to Section 6.2.3 DC CHARACTERISTICS ≤ V When V , memory contents can be read, but PP PPLK not altered can for control pins and addresses, and for V . See Section 6.2.3 PPLK PPH1 PP " ...
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... IA = Identifier code address : see Fig Query offset address Address within the block being erased or locked Address of memory location to be written. 3. SRD = Data read from status register. See Table 13.1 for a description of the status register bits Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first) ...
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... Reserved for Future Use NOTE : 1. X selects the specific block status code to be read. See Fig. 2 for the device identifier code memory map. 4.3 Read Status Register Command The status register may be read to determine when a block erase, full chip erase, (multi) word/byte ...
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The status register may be polled to determine if an error occurs during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied V must ...
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CFI QUERY IDENTIFICATION STRING The identification string provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version OFFSET LENGTH (Word Address) 10H, 11H, 12H 03H Query Unique ASCII string "QRY" 51H, 52H, 59H ...
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DEVICE GEOMETRY DEFINITION This field provides critical details of the flash device geometry. OFFSET LENGTH (Word Address) 27H 01H Device Size 15H (15H = 21, 2 28H, 29H 02H Flash Device Interface Description 02H, 00H (x8/x16 supports x8 and ...
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SCS OEM SPECIFIC EXTENDED QUERY TABLE Certain flash features and commands may be optional in a vendor-specific algorithm specification. The optional vendor-specific query table(s) may be Table 10 SCS OEM Specific Extended Query Table OFFSET LENGTH (Word Address) 31H, ...
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Block Erase Command Block erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by a block erase confirm. This command sequence appropriate sequencing and an address ...
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... Reliable word/byte writes can only occur when V V and the absence of this = CC1 PPH1 high voltage, memory contents are protected against word/byte writes. If word/byte write is ≤ V attempted while V , status register bits PP PPLK SR.3 and SR.4 will be set to "1". Successful word/byte write requires that the corresponding ...
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... SR.1 and SR.4 will be set to "1". IL 4.10 Block Erase Suspend Command The Block Erase Suspend command allows block erase interruption to read or (multi) word/byte write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the ...
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SR.7 will automatically clear and STS will return After the (Multi) Word/Byte Write OL command is written, the device automatically outputs status register data when read (see Fig. 9). V must remain at V (the same ...
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A successful clear block lock-bits operation requires WP attempted with WP SR.1 and SR.5 will be IL set to "1" and the operation will fail. Clear block lock-bits operation with V < ...
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WSMS BESS ECBLBS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE ...
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Start Write 70H Read Status Register 0 SR Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No Erase Loop Suspend 0 SR.7 = Block Erase Yes 1 Full Status Check if Desired Block ...
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Start Write 70H Read Status Register 0 SR Write 30H Write D0H Read Status Register 0 SR Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) ...
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Start Write 70H Read Status Register 0 SR Write 40H or 10H, Address Write Word/Byte Data and Address Read Status Register Suspend Word/Byte No Write Loop Suspend 0 SR.7 = Word/Byte Yes Write 1 Full Status Check if ...
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Start Write E8H, Start Address Read Status Register No 0 Write Buffer XSR.7 = Time-Out 1 Write Word or Byte Count ( Start Address Write Buffer Data, Start Address Abort Yes Write Another Buffer Write ...
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FULL STATUS CHECK PROCEDURE FOR MULTI WORD/BYTE WRITE OPERATION Read Status Register 1 SR Range Error SR.1 = Device Protect Error 0 1 Command Sequence SR. Error 0 1 Multi Word/Byte Write SR.4 ...
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Start Write B0H Read Status Register Read (Multi) Word/Byte Write Read or Write? (Multi) Word/Byte Write Read Array Data No Loop Done? Yes Write D0H Block Erase Resumed Fig. 8 Block Erase ...
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Start Write B0H Read Status Register 0 SR (Multi) Word/Byte Write SR.2 = Completed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read (Multi) Word/Byte Write Array Data Resumed Fig. 9 ...
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Start Write 60H, Block Address Write 01H, Block Address Read Status Register 0 SR Full Status Check if Desired Set Block Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range ...
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Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three- line control provides for : a. Lowest possible memory power consumption. b. Complete assurance that data bus contention will not occur. ...
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... V , the CUI must be placed PPLK in read array mode via the Read Array command if subsequent access to the memory array is desired. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block and full chip erasure, (multi) word/byte writing or block lock-bit configuration during power transitions ...
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... LH28F160S5-L During Read, Erase, Write and Block Lock-Bit Configuration ... 0 to +70°C Temperature under Bias ............. –10 to +80°C • LH28F160S5H-L During Read, Erase, Write and Block Lock-Bit Configuration .... –40 to +85°C Temperature under Bias ............. –40 to +85°C Storage Temperature ........................ –65 to +125°C Voltage On Any Pin ) ..... – ...
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... Output timing ends TTL IH (Standard Testing Configuration) Test Configuration Capacitance Loading Value TEST CONFIGURATION V = 5.0±0. 5.0±0 NOTE : 1. Applied to high-speed products, LH28F160S5-L70 and = 3.3 k LH28F160S5H-L70. L OUT LH28F160S5-L/S5H-L 1.5 OUTPUT = 5.0±0. 2.0 OUTPUT 0.8 (0. for a Logic "0". Input timing TTL and V ...
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... Input Load Current LI I Output Leakage Current Standby Current CCS CC V Deep Power- LH28F160S5 CCD Down Current LH28F160S5H Read Current CCR CC V Write Current CC I CCW ((Multi) W/B Write or Set Block Lock-Bit) V Erase Current CC I (Block Erase, Full Chip Erase, ...
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DC CHARACTERISTICS (contd.) SYMBOL PARAMETER V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL Output High Voltage V OH1 (TTL) Output High Voltage V OH2 (CMOS) V Lockout Voltage during PP V PPLK ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS [LH28F160S5-L] • 5.0±0.25 V, 5.0±0.5V +70° VERSIONS SYMBOL PARAMETER t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV ...
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... See Fig. 13 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing after the falling Load Circuit" (Standard Configuration) for testing GLQV . characteristics LH28F160S5-L/S5H-L (NOTE1) (NOTE 5) LH28F160S5H-L10 MIN. MAX. MIN. MAX. 90 100 90 100 90 100 400 400 ...
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Standby V IH ADDRESSES ( CE# ( OE# ( WE# ( High Z DATA (D/ RP# (P) V ...
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Standby V IH ADDRESSES ( CE# ( OE# ( BYTE# ( High Z DATA (D/Q) (DQ - ...
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AC CHARACTERISTICS - WRITE OPERATIONS [LH28F160S5-L] • 5.0±0.25 V, 5.0±0 VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV RP# High Recovery to WE# t PHWL Going Low t CE# Setup to WE# Going ...
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... See Fig. 13 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing for block erase, Load Circuit" (Standard Configuration) for testing IN characteristics LH28F160S5-L/S5H-L (NOTE 1) (NOTE 6) (NOTE 6) LH28F160S5H-L70 LH28F160S5H-L10 MIN. MAX. MIN. MAX. 90 100 100 100 100 ...
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V IH ADDRESSES ( CE# ( ELWL V IH OE# ( WE# ( High Z DATA (D/ PHWL IL ...
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ALTERNATIVE CE#-CONTROLLED WRITES [LH28F160S5-L] • 5.0±0.25 V, 5.0±0 VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV RP# High Recovery to CE# t PHEL Going Low t WE# Setup to CE# Going Low WLEL ...
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... Load Circuit" (High Speed Configuration) for testing characteristics. 6. See Fig. 13 "Transient Input/Output Reference for block erase, Waveform" and Fig. 14 "Transient Equivalent Testing IN Load Circuit" (Standard Configuration) for testing characteristics LH28F160S5-L/S5H-L (NOTE 1) (NOTE 6) (NOTE 6) LH28F160S5H-L70 LH28F160S5H-L10 MIN. MAX. MIN. MAX. 90 100 100 ...
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V IH ADDRESSES ( WE# ( WLEL V IH OE# ( CE# ( High Z DATA (D/ PHEL IL ...
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RESET OPERATIONS High Z STS ( RP# ( High Z STS ( RP# ( RP# (P) V ...
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BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK LOCK-BIT CONFIGURATION PERFORMANCE • 5.0±0.25 V, 5.0±0 SYMBOL PARAMETER t WHQV1 Word/Byte Write Time (using W/B write, in word mode) t EHQV1 t ...
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... LH28F160S5X-L70 2 LH28F160S5HX-L70 3 LH28F160S5XX-L10 Access Speed (ns (5.0 0.25 V (5.0 0.5 V) [LH28F160S5-L (5.0 0.5 V) [LH28F160S5H- 100 ns (5.0 0.5 V) Package T = 56-pin TSOP (I) (TSOP056-P-1420) Normal bend R = 56-pin TSOP (I) (TSOP056-P-1420) Reverse bend NS = 56-pin SSOP (SSOP056-P-0600) [LH28F160S5- 64-ball CSP (FBGA064-P-0811 64-pin SDIP (SDIP064-P-0750) Under development ...
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TSOP (TSOP056-P-1420 0.3 20.0 18.4 0.2 0.3 19.0 PACKAGING Package base plane ...
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SSOP (SSOP056-P-0600) _ 0 0.15 M TYP 0.2 23.7 Package base plane 0.10 PACKAGING 0.05 0.15 ...
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CSP (FBGA064-P-0811 0.1 S TYP. 2.7 TYP. 0.8 TYP. 0 TYP 0.2 11 0.03 0. ...
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Package Outline 64 SDIP (SDIP064-P-0750 0.3 58.0 0.1 1.778 TYP. 0.46 (Unit : mm 19.05 TYP. 0.25 M PACKAGING SDIP : Shrink DIP SOP : Small Outline Package SSOP: Shrink SOP TSOP : Thin SOP CSP ...