dsm2180f3v STMicroelectronics, dsm2180f3v Datasheet - Page 50

• Manufacturer Part Number: dsm2180f3v
• Description: Dsm Digital Signal Processor System Memory For Analog Devices Adsp-218x Family 3.3v Supply
• Manufacturer: STMicroelectronics

DSM2180F3V
Table 28. CPLD Macrocell Synchronous Clock Mode Timing
Note: 1. Fast Slew Rate output available on PB3-PB0, and PD2-PD0.
Table 29. CPLD Macrocell Asynchronous Clock Mode Timing
50/63
f
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
Symbol
Symbol
MAX
S
H
CH
CL
CO
ARD
MIN
MAXA
SA
HA
CHA
CLA
COA
ARD
MINA
2. CLKIN (PD1) t
Maximum Frequency
External Feedback
Maximum Frequency
Internal Feedback (f
Maximum Frequency
Pipelined Data
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
Maximum Frequency
External Feedback
Maximum Frequency
Internal Feedback (f
Maximum Frequency
Pipelined Data
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
Parameter
Parameter
CLCL
= t
CH
+ t
CNT
CNTA
CL
2
.
)
)
1/(t
Any Macrocell
Any Macrocell
1/(t
1/(t
1/(t
Conditions
Conditions
Clock Input
Clock Input
Clock Input
1/(t
1/(t
SA
t
1/f
S
CHA
CH
SA
+t
+t
CH
S
CNTA
+t
CO
+t
+t
COA
+t
+t
CO
CL
COA
–10)
CL
CLA
–10)
)
)
)
)
Min
Min
25
15
15
29
12
15
22
15
42
0
-15
-15
Max
18.8
23.2
33.3
Max
19.2
23.8
28
29
27
40
29
Add 4
Add 4
Add 4
Add 4
Aloc
Aloc
PT
PT
Add 20
Add 20
Add 20
Add 20
Add 20
Turbo
Turbo
Off
Off
Rate
Sub 6
Sub 6
Slew
Slew
Rate
1
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns