s-24c04bphal Seiko Instruments Inc., s-24c04bphal Datasheet - Page 25
s-24c04bphal
Manufacturer Part Number
s-24c04bphal
Description
2-wire Cmos Serial E2prom
Manufacturer
Seiko Instruments Inc.
Datasheet
1.S-24C04BPHAL.pdf
(35 pages)
- Current page: 25 of 35
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8. Data hold time (t
9. SDA pin and SCL pin noise suppression time
Rev.3.0
If SCL and SDA of the E
condition from being mistakenly recognized due to the effect of noise. If a start/stop condition is mistakenly
recognized during communication, the E
It is recommended that SDA is delayed from the falling edge of SCL by 0.3 µ s minimum in the S-
24C04BPHAL. This is to prevent time lag caused by the load of the bus line from generating the stop (or
start) condition.
The S-24C04BPHAL includes a built-in low-pass filter to suppress noise at the SDA and SCL pins. This
means that if the power supply voltage is 5.0 V (at room temperature), noise with a pulse width of 150 ns or
less can be suppressed.
The guaranteed for details, refer to noise suppression time (t
_00
Noise suppression time (t
HD. DAT
Figure 27 Noise Suppression Time for SDA and SCL Pins
= 0 ns)
[ns]
SDA
SCL
2
PROM are changed at the same time, it is necessary to prevent the start/stop
I
) Max.
Figure 26 E
2
Seiko Instruments Inc.
PROM enters the standby status.
300
200
100
2
PROM Data Hold Time
t
HD. DAT
Power supply voltage (V
= 0.3 µs Min.
2
I
) in Table 9 .
[V]
3
2-WIRE CMOS SERIAL E
4
CC
)
5
S-24C04BPHAL
2
PROM
25
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