s-93c46a Seiko Instruments Inc., s-93c46a Datasheet - Page 7

• Manufacturer Part Number: s-93c46a
• Description: Cmos Serial E2prom
• Manufacturer: Seiko Instruments Inc.

CMOS SERIAL E
S-93C46A/56A/66A
n
edge of SK after CS goes high. A start-bit can only be recognized when the high of DI is latched to the rising edge of SK
when CS goes from low to high, it is impossible for it to be recognized as long as DI is low, even if there are SK pulses after
CS goes high. Any SK pulses input while DI is low are called "dummy clocks." Dummy clocks can be used to adjust the
number of clock cycles needed by the serial IC to match those sent out by the CPU. Instruction input finishes when CS
goes low, where it must be low between commands during t
1. Read
changes from a high-impedance state (Hi-Z) to low level output. Data is continuously output in synchronization with the rise
of SK.
of another SK clock. Thus, it is possible for all of the data addresses to be read through the continuous input of SK clocks
as long as CS is high.
6
CS
SK
DO
CS
SK
DO
DI
DI
Instructions (in the order of start-bit, instruction, address, and data) are latched to DI in synchronization with the rising
All input, including DI and SK signals, is ignored while CS is low, which is stand-by mode.
The READ instruction reads data from a specified address. After A0 is latched at the rising edge of SK, DO output
When all of the data (D0) in the specified address has been read, the data in the next address can be read with the input
The last address (An
Operation
1
1
1
1
1
1
2
2
0
0
3
3
X
A
5
4
4
Hi-Z
2
Hi-Z
A
PROM
A
6
4
5
ŸŸŸ
5
A
A
5
A1 A0 = 1
3
6
6
A
A
4
2
7
7
A
A
3
1
8
8
A
A
2
0
9
9
ŸŸŸ
0
A
10
1
11) rolls over to the top address (An
10
D
15
A
11
0
Figure 4
Figure 5
11
0
D
14
12
12
D
D
15
13
Seiko Instruments Inc.
13
D
14
14
D
Read Timing (S-93C46A)
13
Read Timing (S-93C56A)
23
CDS
D
2
24
24
.
D
A
1
5
A
25
25
D
4
D
A
2
0
3
26
A
A
26
D
D
2
6
15
1
A
A
1
5
27
A
A
27
D
D
0
4
0
14
+1
A
3
28
D
28
A
D
15
2
13
A
ŸŸŸ
29
D
1
A
14
0
A1 A0 = 0
+1
D
13
39
D
2
40
40
D
A
ŸŸŸ
1
5
41
A
41
D
4
00).
0
A
42
3
42
D
A
A
D
15
2
6
1
A
A
43
1
5
43
D
A
D
A
14
0
0
4
+2
A
44
D
44
3
D
A
15
13
2
A
45
D
1
14
A
0
+2
D
13
Hi-Z
Hi-Z