stk14ee8-tf45tr Simtek Corporation, stk14ee8-tf45tr Datasheet - Page 11

• Manufacturer Part Number: stk14ee8-tf45tr
• Description: 1mx8 Autostore Nvsram
• Manufacturer: Simtek Corporation

Document Control #ML0068 Rev 1.0
Preliminary
nvSRAM
The STK14EE8 nvSRAM is made up of two func-
tional components paired in the same physical cell.
These are the SRAM memory cell and a nonvolatile
QuantumTrap cell. The SRAM memory cell operates
like a standard fast static RAM. Data in the SRAM
can be transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to
SRAM (the RECALL operation). This unique archi-
tecture allows all cells to be stored and recalled in
parallel. During the STORE and RECALL operations
SRAM READ and WRITE operations are inhibited.
The STK14EE8 supports unlimited read and writes
like a typical SRAM. In addition, it provides unlimited
RECALL operations from the nonvolatile cells and
up to 1 Million STORE operations.
SRAM READ
The STK14EE8 performs a READ cycle whenever E
and G are low while W and HSB are high. The
address specified on pins A
the 1,048,576 data bytes will be accessed. When
the READ is initiated by an address transition, the
outputs will be valid after a delay of t
cycle #1). If the READ is initiated by E and G, the
outputs will be valid at t
is later (READ cycle #2). The data outputs will
repeatedly respond to address changes within the
t
on any control input pins, and will remain valid until
another address change or until E or G is brought
high, or W and HSB is brought low.
AVQV
v
CC
March, 2008
access time without the need for transitions
Figure 3: AutoStore Mode
v
W
CC
ELQV
0-19
or at t
determine which of
v
CAP
GLQV
nvSRAM OPERATION
AVQV
, whichever
Simtek Confidential
(READ
11
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into memory if it is valid t
before the end of a W controlled WRITE or t
before the end of an E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
low.
AutoStore OPERATION
The STK14EE8 stores data to nvSRAM using one of
three storage operations. These three operations
are Hardware Store (activated by HSB), Software
Store (activated by an address sequence), and
AutoStore (on power down).
AutoStore operation is a unique feature of Simtek
Quantum Trap technology that is enabled by default
on the STK14EE8.
During normal operation, the device will draw cur-
rent from V
the V
chip to perform a single STORE operation. If the
voltage on the V
part will automatically disconnect the V
V
provided by the V
Figure 3 shows the proper connection of the storage
capacitor (V
voltage on the V
lator internal to the chip. Refer to the DC CHARAC-
TERISTICS table for the size of the capacitor. A pull
up should be placed on W to hold it inactive during
power up. This pull-up is only effective if the W sig-
nal is tri-state during power up. Many MPU’s will tri-
state their controls on power up. This should be ver-
ified when using the pullup. When the nvSRAM
comes out on power-on-recall, the MPU must be
active or the W held inactive until the MPU comes
out of reset.
CC
. A STORE operation will be initiated with power
CAP
pin. This stored charge will be used by the
CC
CAP
to charge a capacitor connected to
) for automatic store operation. The
CAP
CC
CAP
pin is driven to 3.6V by a regu-
pin drops below V
capacitor.
WLQZ
STK14EE8
after W goes
CAP
SWITCH
pin from
DVWH
DVEH
, the