m5m5v5636gp-16 Renesas Electronics Corporation., m5m5v5636gp-16 Datasheet

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m5m5v5636gp-16

Manufacturer Part Number
m5m5v5636gp-16
Description
18874368-bit 524288-word By 36-bit Network Sram
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Part Number:
m5m5v5636gp-161
Manufacturer:
MARONIX
Quantity:
544
DESCRIPTION
SRAMs organized as 524288-words by 36-bit. It is designed to
eliminate dead bus cycles when turning the bus around between
reads and writes, or writes and reads. Renesas's SRAMs are
fabricated with high performance, low power CMOS technology,
providing greater reliability. M5M5V5636GP operates on 3.3V
power/ 2.5V I/O supply or a single 3.3V power supply and are
3.3V CMOS compatible.
supply and is also 2.5V CMOS compatible. Therefore the
M5M5V5636GP can replace the M5M5T5636GP.
is guaranteed both AC DC electrical characteristics of 167MHz
and those of 133MHz.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 167 MHz and 133MHz
• Fast access time: 3.8 ns and 4.2ns
• Single 3.3V -5% and +5% power supply V
• Separate V
• Single 2.5V -5% and +5% power supply V
• Individual byte write (BWa# - BWd#) controls may be tied
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• Three chip enables for simple depth expansion
PART NAME
1/18
LOW
to control G#
The M5M5V5636GP is a family of 18M bit synchronous
The M5M5V5636GP also operates on a single 2.5V power
The M5M5V5636GP-16 operates at 167MHz or 133MHz and
M5M5V5636GP-16
DDQ
Operate frequency
for 3.3V or 2.5V I/O
167MHz
133MHz
Access
3.8ns
4.2ns
DD
DD
6.0ns
7.5ns
Cycle
PACKAGE
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers
FUNCTION
triggered by a positive edge clock transition.
all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
BWd#) and Read/Write (W#). Write operations are controlled by
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)
inputs. All writes are conducted with on-chip synchronous
self-timed write circuitry.
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the
SRAM in the power-down state.The Linear Burst order (LBO#) is
DC operated pin. LBO# pin will allow the choice of either an
interleaved burst, or a linear burst.
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
Synchronous circuitry allows for precise cycle control
Synchronous signals include : all Addresses, all Data Inputs,
Asynchronous inputs include Output Enable (G#), Clock (CLK)
All read, write and deselect cycles are initiated by the ADV
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
100pin TQFP
Active Current
380mA
350mA
(max.)
.
M5M5V5636GP –16
Standby Current
M5M5V5636GP-16 REV.2.0
30mA
30mA
(max.)
Renesas LSIs

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m5m5v5636gp-16 Summary of contents

Page 1

... CMOS compatible. The M5M5V5636GP also operates on a single 2.5V power supply and is also 2.5V CMOS compatible. Therefore the M5M5V5636GP can replace the M5M5T5636GP. The M5M5V5636GP-16 operates at 167MHz or 133MHz and is guaranteed both AC DC electrical characteristics of 167MHz and those of 133MHz. FEATURES • Fully registered inputs and outputs for pipelined operation • ...

Page 2

... Note1. MCH means "Must Connect High". MCH should be connected to HIGH. 2/18 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM M5M5V5636GP Renesas LSIs M5M5V5636GP –16 50 A10 49 A11 48 A12 47 A13 46 A14 45 A15 44 A16 VDD 40 VSS LBO# M5M5V5636GP-16 REV.2.0 ...

Page 3

... AND DATA COHERENCY CONTROL LOGIC READ LOGIC V SS M5M5V5636GP –16 BYTE1 WRITE DRIVERS BYTE2 256Kx36 WRITE DRIVERS MEMORY BYTE3 ARRAY WRITE DRIVERS BYTE4 WRITE DRIVERS INPUT INPUT 36 REGISTER1 REGISTER0 M5M5V5636GP-16 REV.2.0 Renesas LSIs DQa DQPa DQb DQPb DQc DQPc DQd DQPd ...

Page 4

... HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input leak current to this pin. Core Power Supply Core Ground I/O buffer Power supply I/O buffer Ground These pins should be connected to HIGH These pins are not internally connected and may be connected to ground. Renesas LSIs M5M5V5636GP –16 Function M5M5V5636GP-16 REV.2.0 ...

Page 5

... Next Write Cycle, Begin Burst D External Write Cycle, Continue Burst D Next NOP/Write Abort, Begin Burst High-Z None Write Abort, Continue Burst High-Z Next Ignore Clock edge, Stall - Current Snooze Mode High-Z None M5M5V5636GP-16 REV.2 ...

Page 6

... Read Begin Burst Read Continue Burst Input Command Code Transition f Current State M5M5V5636GP – Write Begin Burst Write Continue Burst Next State M5M5V5636GP-16 REV.2.0 Renesas LSIs ...

Page 7

... Read X Write Byte a H Write Byte b H Write Byte c H Write Byte d L Write All Bytes L Write Abort/NOP H Conditions With respect +0.5V in case of DC. DDQ Renesas LSIs M5M5V5636GP –16 Ratings Unit -1.0*~4.6 V -1.0*~4.6 V -1.0~V +1.0** V DDQ -1.0~V +1.0** V DDQ 1.6 W 0~70 °C -10~85 °C -65~150 °C M5M5V5636GP-16 REV.2.0 ...

Page 8

... V V -0.2V I DDQ +1.0V in case of AC(Pulse width 2ns). DDQ Renesas LSIs M5M5V5636GP –16 Limits Unit Min Max 3.135 3.465 V 3.135 3.465 V 2.375 2.625 2.0 V +0.3* V DDQ 1.7 0.8 -0.3* V 0.7 V -0.4 V DDQ 0 µA 100 100 10 µA 380 mA 350 160 mA 130 130 mA 120 M5M5V5636GP-16 REV.2.0 ...

Page 9

... I SS 7.5ns cycle(133MHz -0.2V I DDQ +1.0V in case of AC(Pulse width 2ns). DDQ Renesas LSIs M5M5V5636GP –16 Limits Unit Min Max 2.375 2.625 V 2.375 2.625 V 1.7 V +0.3* V DDQ -0.3* 0 -0.4 V DDQ 0 µA 100 100 10 µA 380 mA 350 160 mA 130 130 mA 120 M5M5V5636GP-16 REV.2.0 ...

Page 10

... Min Typ Limits Min Typ 28 20 6.6 =2.375~2.625V, unless otherwise noted DDQ toff ton Vh-(0.2(Vh-Vz)) Vz+(0.2(Vh-Vz)) (toff) Vz 0.2(Vz-Vl) Vz-(0.2(Vz-Vl)) Fig.3 Tri-State measurement /2 on the output waveform. DDQ 1V/ns. faster than or equal to M5M5V5636GP-16 REV.2.0 Renesas LSIs Unit Max Unit Max °C/W °C/W °C/W (ton) 1V/ns. ...

Page 11

... ZZ=LOW fix. are sampled. Renesas LSIs M5M5V5636GP –16 Limits 167MHz 133MHz -16 -16 Min Max Min Max 6.0 7.5 2.7 3.0 2.7 3.0 3.8 4.2 1.5 1.5 1.5 1.5 1.5 3.8 1.5 4.2 3.8 4.2 0.0 0.0 3.8 4.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 2*t 2*t KHKH KHKH 2*t 2*t KHKH KHKH M5M5V5636GP-16 REV.2.0 Unit ...

Page 12

... Note30. E# represents three signals. When E# is LOW, it represents E1# is LOW HIGH and E3# is LOW. Note31.ZZ is fixed LOW . 12/18 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM t KLKH Q(A1) Q(A2) Q(A2+1) Q(A2+2) t GHQZ t KHQX Stall Burst Read Burst Read Burst Read A2+1 A2+2 A2+3 A2 M5M5V5636GP – GLQV Q(A2+3) Q(A2) t KHQZ t GLQX1 Deselect Continue Read A3 Burst Read Burst Read Deselect A3+1 DON'T CARE M5M5V5636GP-16 REV.2.0 Renesas LSIs Q(A3) Q(A3+1) Burst Read A3+2 A3+3 UNDEFINED ...

Page 13

... Note33. E# represents three signals. When E# is LOW, it represents E1# is LOW HIGH and E3# is LOW. Note34.ZZ is fixed LOW. 13/18 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM t KLKH A3 t KHDX D(A1) D(A2) D(A2+1) D(A2+3) NOP Burst Write Write A2 Write A3 A2+1 A2+3 Renesas LSIs M5M5V5636GP –16 A4 D(A2) D(A3) D(A4) Write A4 NOP Burst Write Stall Burst Write A4+1 A4+2 DON'T CARE M5M5V5636GP-16 REV.2.0 D(A4+1) Burst Write A4+3 UNDEFINED ...

Page 14

... Note36. E# represents three signals. When E# is LOW, it represents E1# is LOW HIGH and E3# is LOW. Note37.ZZ is fixed LOW. 14/18 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM t KLKH DVKH t KHDX Q(A1) D(A2) Q(A2) D(A3) D(A3+1) t KHQV Write A3 Burst Write Read A3 Burst Read A3+1 A3+1 M5M5V5636GP – Q(A3) Q(A3+1) D(A4) Deselect Write A4 Stall Read A5 Burst Read A5+1 DON'T CARE M5M5V5636GP-16 REV.2.0 Renesas LSIs Q(A5) Burst Read A5+2 UNDEFINED ...

Page 15

... MODE TIMING CLK t ZZS ZZ All Inputs (except ZZ) Q 15/18 M5M5V5636GP –16 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM t ZZREC DESELECT or READ only Snooze Mode Renesas LSIs M5M5V5636GP-16 REV.2.0 ...

Page 16

... Nom Note38. Dimensions *1 and *2 don't include mold flash. Note39 Dimension *3 doesn't include trim off set. Note40.All dimensions in millimeters. 16/18 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM 0.32+0.06 -0.07 0.1 0.13 M M5M5V5636GP –16 0.125+0.05 -0.02 0.5±0.15 Detail A M5M5V5636GP-16 REV.2.0 Renesas LSIs 0°~7° ...

Page 17

... Maximum Power Dissipation) 17/18 M5M5V5636GP –16 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM Date June 4, 2001 July 16, 2001 March 28, 2002 July 5, 2002 August 6, 2002 January 14, 2003 August 1, 2003 March 15, 2004 from 1180mW to 1.6W Renesas LSIs Advanced Information Advanced Information Advanced Information Preliminary Preliminary Preliminary Preliminary M5M5V5636GP-16 REV.2.0 ...

Page 18

... Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. REJ03C0074 © 2003 Renesas Technology Corp. New publication, effective March 2004. Specifications subject to change without notice. M5M5V5636GP –16 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM Renesas LSIs ...

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