m5m5v5636gp-13i Renesas Electronics Corporation., m5m5v5636gp-13i Datasheet - Page 4

• Manufacturer Part Number: m5m5v5636gp-13i
• Description: 18874368-bit 524288-word By 36-bit Network Sram
• Manufacturer: Renesas Electronics Corporation.

January 31, 2003
Preliminary
Notice: This is not final specification.
Some parametric limits are subject to change.
DESCRIPTION
The M5M5V5636GP is a family of 18M bit synchronous SRAMs
organized as 524288-words by 36-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Mitsubishi's SRAMs are
fabricated with high performance, low power CMOS technology,
providing greater reliability. M5M5V5636GP operates on 3.3V
power/ 2.5V I/O supply or a single 3.3V power supply and are
3.3V CMOS compatible.
FEATURES
• Supported Industrial Temperature Range
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 167 MHz and 133MHz
• Fast access time: 3.8 ns and 4.2ns
• Single 3.3V -5% and +5% power supply V
• Separate V
• Individual byte write (BWa# - BWd#) controls may be tied
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• Three chip enables for simple depth expansion
Package
PART NAME TABLE
1/17
LOW
to control G#
100pin TQFP
M5M5V5636GP – 16I
M5M5V5636GP – 13I
DDQ
for 3.3V or 2.5V I/O
Part Name
Rev.0.1
Access
DD
3.8ns
4.2ns
6.0ns
7.5ns
Cycle
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers
FUNCTION
triggered by a positive edge clock transition.
all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
BWd#) and Read/Write (W#). Write operations are controlled by
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)
inputs. All writes are conducted with on-chip synchronous
self-timed write circuitry.
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the
SRAM in the power-down state.The Linear Burst order (LBO#) is
DC operated pin. LBO# pin will allow the choice of either an
interleaved burst, or a linear burst.
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
Synchronous circuitry allows for precise cycle control
Synchronous signals include : all Addresses, all Data Inputs,
Asynchronous inputs include Output Enable (G#), Clock (CLK)
All read, write and deselect cycles are initiated by the ADV
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
Active Current
380mA
350mA
(max.)
M5M5V5636GP –16I,13I
.
Standby Current
M5M5V5636GPI REV.0.1
(max.)
30mA
30mA
MITSUBISHI LSIs
Preliminary