nm93c66 Fairchild Semiconductor, nm93c66 Datasheet
nm93c66
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nm93c66 Summary of contents
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... CMOS process for high reliability, high endurance and low power consumption. “LZ” and “L” versions of NM93C66 offer very low standby current making them suitable for low power applications. This device is offered in both SO and TSSOP packages for small space consid- erations ...
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... Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the NM93C66 Rev ...
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... CSH t DI Hold Time DIH t Output Delay Status Valid Hi Write Cycle Time WP NM93C66 Rev. E (Note 1) -65°C to +150°C Ambient Operating Temperature NM93C66 +6.5V to -0.3V NM93C66E NM93C66V +300°C Power Supply ( 2000V V = 4.5V to 5.5V unless otherwise specified SK=1 ...
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... MHz (Note Output Capacitance OUT C Input Capacitance IN 2.7V ≤ V ≤ 5.5V 0.3V/1.8V CC (Extended Voltage Levels) 4.5V ≤ V ≤ 5.5V 0.4V/2.4V CC (TTL Levels) NM93C66 Rev. E (Note 1) -65°C to +150°C Ambient Operating Temperature NM93C66L/LZ +6.5V to -0.3V NM93C66LE/LZE NM93C66LV/LZV +300°C Power Supply ( 2000V V = 2.7V to 5.5V unless otherwise specified SK=1.0 MHz ...
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... This is an 8-bit field and should immediately follow the Opcode bits. In NM93C66, all 8 bits are used for address decoding during READ, WRITE and ERASE instructions. During all other instructions, the MSB 2 bits are used to decode instruction (along with Opcode bits). ...
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... DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. NM93C66 Rev. E The status of the internal programming cycle can be polled at any time by bringing the CS signal high again, after t CS signal is high, the DO pin indicates the READY/BUSY status of the chip ...
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... ALL” instruction, respectively. The “ERASE” and “ERASE ALL” instructions are included to maintain compatibility with earlier technology EEPROMs.Clearing of Ready/Busy status NM93C66 Rev. E When programming is in progress, the Data-Out pin will display the programming status as either BUSY (low) or READY (high) when CS is brought high (DO output will be tri-stated when CS is low) ...
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... WRITE ENABLE CYCLE (WEN > > NM93C66 Rev SKH SKL t DIH Valid Input t ...
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... > > > NM93C66 Rev ...
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... Address bits patter n -> 1-0-x-x-x-x-x-x CLEARING READY STATUS High - Z DO Note: This Star t bit can also be par next instr uction. Hence the cycle can be continued (instead of getting ter minated, as shown new instr uction is being issued. NM93C66 Rev ...
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... All lead tips Typ. All Leads NM93C66 Rev. E 0.189 - 0.197 (4.800 - 5.004 0.228 - 0.244 (5.791 - 6.198 Lead #1 IDENT 0.053 - 0.069 (1.346 - 1.753) 8° ...
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... Pin #1 IDENT 0.0433 Max (1.1) 0.0256 (0.65) Typ. Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93 NM93C66 Rev 0.169 - 0.177 (4.30 - 4.50) (1.78) Typ (0.42) Typ Land pattern recommendation 4 See detail A 0.002 - 0.006 (0.05 - 0.15) 0.0075 - 0.0098 (0.19 - 0.30) 0°-8° DETAIL A Typ. Scale: 40X ...
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... English Français Italiano Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. NM93C66 Rev. E 0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) ...