nm93c46 Fairchild Semiconductor, nm93c46 Datasheet - Page 4

• Manufacturer Part Number: nm93c46
• Description: 1024-bit Serial Cmos Eeprom Microwire ?ynchronous Bus
• Manufacturer: Fairchild Semiconductor

NM93C46 Rev. E
Ambient Storage Temperature
All Input or Output Voltages
Lead Temperature
ESD rating
(Extended Voltage Levels)
C
2.7V ≤ V
4.5V ≤ V
C
with Respect to Ground
(Soldering, 10 sec.)
OUT
I
I
V
t
t
t
V
t
t
t
t
t
V
V
t
t
t
CCA
CCS
I
f
SKH
SKS
CSS
CSH
t
t
IN
SKL
DIH
I
DIS
WP
OL
SK
CS
DH
PD
SV
DF
IL
OH
OL
IH
IL
(TTL Levels)
CC
CC
Output Capacitance
≤ 5.5V
≤ 5.5V
Input Capacitance
Operating Current
Standby Current
L
LZ (2.7V to 4.5V)
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
Minimum CS Low Time
CS Setup Time
DO Hold Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
T
A
= 25°C, f = 1 MHz (Note 5)
0.3V/1.8V
0.4V/2.4V
(Note 1)
-65°C to +150°C
Output Load: 1 TTL Gate (C
+6.5V to -0.3V
5
5
CS = V
CS = V
(Note 2)
(Note 3)
(Note 4)
CS = V
V
I
I
OL
OH
IN
+300°C
2000V
= 10µA
= -10µA
= 0V to V
pF
pF
V
IH
IL
IL
1.0V/2.0V
CC
, SK=1.0 MHz
1.0V
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both t
allowable to set 1/f
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
= 2.7V to 5.5V unless otherwise specified
CC
Ambient Operating Temperature
Power Supply (V
:
:
:
:
:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
Typical leakage values are in the 20nA range.
The shortest allowable SK clock period = 1/f
CS (Chip Select) must be brought low (to V
This parameter is periodically sampled and not 100% tested.
NM93C46L/LZ
NM93C46LE/LZE
NM93C46LV/LZV
L
= 100 pF)
SK
= t
SKHminimum
CC
0.8V/1.5V
0.4V/2.4V
)
+ t
SKLminimum
0.8V
0.9V
-0.1
0.2
0.2
0.4
0.4
70
0
1
1
1
0
SKH
CC
CC
for shorter SK cycle time operation.
and t
IL
SK
) for an interval of t
SKL
(as shown under the f
limits must be observed. Therefore, it is not
0.15V
V
0.1V
CC
250
0.4
10
±1
15
1
1
2
1
+1
CC
CC
2.1mA/-0.4mA
CS
in order to reset all internal
-40°C to +125°C
±10µA
SK
www.fairchildsemi.com
-40°C to +85°C
parameter). Maximum
0°C to +70°C
2.7V to 5.5V
KHz
mA
ms
µA
µA
µA
µs
µs
µs
µs
µs
ns
µs
ns
µs
µs
µs
µs
V
V