nm93c86a Fairchild Semiconductor, nm93c86a Datasheet
nm93c86a
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nm93c86a Summary of contents
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... Semiconductor floating-gate CMOS process for high reliability, high endurance and low power consumption. “LZ” and “L” versions of NM93C86A offer very low standby current making them suitable for low power applications. This device is offered in both SO and TSSOP packages for small space consid- erations ...
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... Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the NM93C86A Rev. F ...
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... CSH t DI Hold Time DIH t Output Delay Status Valid Hi Write Cycle Time WP NM93C86A Rev. F.1 (Note 1) -65°C to +150°C Ambient Operating Temperature NM93C86A +6.5V to -0.3V NM93C86AE NM93C86AV +300°C Power Supply ( 2000V V = 4.5V to 5.5V unless otherwise specified SK=1 ...
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... MHz (Note Output Capacitance OUT C Input Capacitance IN 2.7V ≤ V ≤ 5.5V 0.3V/1.8V CC (Extended Voltage Levels) 4.5V ≤ V ≤ 5.5V 0.4V/2.4V CC (TTL Levels) NM93C86A Rev. F.1 (Note 1) -65°C to +150°C Ambient Operating Temperature NM93C86AL/LZ +6.5V to -0.3V NM93C86ALE/LZE NM93C86ALV/LZV +300°C Power Supply ( 2000V V = 2.7V to 5.5V unless otherwise specified SK=1.0 MHz ...
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... This is an active high input pin to NM93C86A EEPROM (the device) and is generated by a master that is controlling the device. A high level on this pin selects the device and a low level deselects the device. All serial communications with the device is enabled only when this pin is held high. However this pin cannot be permanently ...
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... Opcode and Address) for this WEN instruction should be issued as listed under Table 1 or Table 2. The device becomes write- enabled at the end of this cycle when the CS signal is brought low. Execution of a READ instruction is independent of WEN instruc- tion. Refer Write Enable cycle diagram. NM93C86A Rev. F.1 Opcode Field Address Field 10 A10 A9 ...
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... Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table 1 or Table NM93C86A Rev. F.1 2. After inputting the last bit of data (A0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle ...
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... > > =A10 > > NM93C86A Rev. F SKH SKL t DIH ...
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... > > NM93C86A Rev. F ...
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... NM93C86A Rev. F ...
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... All lead tips Typ. All Leads NM93C86A Rev. F.1 0.189 - 0.197 (4.800 - 5.004 0.228 - 0.244 (5.791 - 6.198 Lead #1 IDENT 0.053 - 0.069 (1.346 - 1.753) 8° ...
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... Pin #1 IDENT 0.0433 Max (1.1) 0.0256 (0.65) Typ. Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93 NM93C86A Rev. F.1 5 0.169 - 0.177 (4.30 - 4.50) (1.78) Typ (0.42) Typ Land pattern recommendation 4 See detail A 0.002 - 0.006 (0.05 - 0.15) 0.0075 - 0.0098 (0.19 - 0.30) 0°-8° DETAIL A Typ. Scale: 40X ...
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... English Français Italiano Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. NM93C86A Rev. F.1 0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) ...