m36dr232a STMicroelectronics, m36dr232a Datasheet - Page 14

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m36dr232a

Manufacturer Part Number
m36dr232a
Description
32 Mbit 2mb X16, Dual Bank, Page Flash Memory And 2 Mbit 128k X16 Sram, Multiple Memory Product
Manufacturer
STMicroelectronics
Datasheet

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M36D232A, M36DR232B
Table 14. Protection States
Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WPF status.
Table 15. Instructions
14/46
Current State
(WP, DQ1, DQ0)
RD
AS
Mne.
RCFI
DPG
EBY
CR
PG
2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by
3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WPF has
4. A WPF transition to V
(4)
(4)
100
101
000
001
110
011
111
DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Autoselect instruction with A1 = V
changed its logic value.
Read/Reset
Memory Array
CFI Query
Auto Select
Configuration
Register Write
Program
Double Word
Program
Enter Bypass
Mode
(2)
Instr.
Program/Erase
Allowed
IH
(1,2)
yes
yes
yes
no
no
no
no
on a locked block will restore the previous DQ0 value, giving a 111 or 110.
Cyc.
1+
3+
1+
3+
4
4
5
3
(1)
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
(3)
Protect
101
101
001
001
011
111
111
1st Cyc.
555h
555h
555h
555h
555h
555h
AAh
AAh
AAh
AAh
AAh
AAh
F0h
55h
98h
X
Read Memory Array until a new write cycle is initiated.
Read CFI data until a new write cycle is initiated.
2nd Cyc.
2AAh
2AAh
2AAh
2AAh
2AAh
2AAh
Unprotect
55h
55h
55h
55h
55h
55h
Next State After Event
100
100
110
110
000
000
011
3rd Cyc.
555h
555h
555h
555h
555h
555h
A0h
F0h
90h
60h
40h
20h
Read Memory Array until a new
write cycle is initiated.
Read electronic Signature or
Block Protection or Configuration
Register Status until a new cycle
is initiated.
Configura-
tion Data
Address 1
4th Cyc.
Program
Program
Program
Program
Address Read Data Polling or
Data 1
Lock
Data
011
011
011
111
111
111
111
03h
(3)
Toggle Bit until
Program completes.
Address 2
5th Cyc.
Program
Program
Data 2
WP transition
111 or 110
IH
and A0 = V
000
001
011
011
100
101
Note 6, 7
6th Cyc.
(4)
IL
.

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