ncp1231d65r2g ON Semiconductor, ncp1231d65r2g Datasheet - Page 16

• Manufacturer Part Number: ncp1231d65r2g
• Description: Lowstandby Power High Performance Pwm Controller
• Manufacturer: ON Semiconductor

Drive Output
connected through a current limiting resistor to the gate of
a MOSFET. The Driver output is capable of delivering drive
pulses with a rise time of 40 ns, and a fall time of 15 ns
through its internal source and sink resistance of 12.3 ohms
(typical), measured with a 1.0 nF capacitive load.
Startup Sequence
outlet, current flows through Rstartup, charging the Vcc
capacitor (refer to Figure 37). When the voltage on the Vcc
capacitors reaches VccON level (typically 12.6 V), the
NCP1231 then turns on the drive output to the external
MOSFET in an attempt to increase the output voltage and
charge up the Vcc capacitor through the Vaux winding in the
transformer.
maximum peak current, which is reached after the 5 ms
softïstart period (adjustable). As soon as the maximum peak
set point is reached, the internal 1.0 V clamp actively limits
the current amplitude to 1.0 V/Rsense and asserts an error
flag indicating that a maximum current condition is being
observed. In this mode, the controller must determine if it is
a normal startup period (or transient load) or is the controller
is facing a fault condition. To determine the difference
between a normal startup sequence, and a fault condition, the
error flag is asserted, and the 100 ms timer starts to count
down. If the error flag drops prior to the 100 ms timeïout
period, the controller resets the timer and determines that it
was a normal starïup sequence and enables the low
impedance switch (SW1), enabling the PFC_Vcc output.
asserted, then the controller assumes that it is a fault
condition and the PWM controller enters the skip mode and
does not enable the PFC_Vcc output.
The NCP1231 provides a Drive Output which can be
When the power supply is first connected to the mains
During the startup sequence, the controller pushes for the
If at the end of the 100 ms period the error flag is still
2
FB
20k
Vdd
10 V
55k
25k
Skip
Comparators
http://onsemi.com
+
−
Figure 38.
NCP1231
SoftïStart
Ramp (1V max)
16
SoftïStart
soon as Vcc reaches a nominal 12.6 V, the softïstart circuit
is activated. The softïstart circuit output controls a reference
on the minus (ï) input to an amplifier (refer to Figure 38),
the positive (+) input to the amplifier is the feedback input
(divided by 3). The output of the amplifier drives a FET
which clamps the feedback signal. As the softïstart circuit
output ramps up, it allow the feedback pin input to the PWM
comparator to gradually increased from near zero up to the
maximum clamping level of 1 V/Rsense. This occurs over
the entire 5 ms softïstart period until the supply enters
regulation. The softïstart is also activated every time a
restart is attempted. Figure 39 shows a typical softïstart up
sequence (with softïstart), normal operation (frequency
jittering), and a confirmed over load conditon (100 msec
timeout).
UVLO
The NCP1231 features an adjustable softïstart circuit. As
Error
ï
+
5 msec
+
Timer
Vdd
12.6 V /
7.7 V
max
30 mA
6
4
Figure 37.
CS
High Voltage
+
Rstartup
CVcc
OSC
−
+
PWM
Auxliary
winding