ncp1232dr2 ON Semiconductor, ncp1232dr2 Datasheet - Page 4

• Manufacturer Part Number: ncp1232dr2
• Description: Microprocessor Monitor
• Manufacturer: ON Semiconductor

Power Monitor
conditions and warns a processor–based system of an
impending power failure. When V CC is detected as below
the preset level defined by TOL, the V CC comparator
outputs the signals RST and RST. If TOL is connected to
ground, the RST and RST signals become active as V CC falls
below 4.75 volts. If TOL is connected to V CC , the RST and
RST become active as V CC falls below 4.5 volts. Because
the processing is stopped at the last possible moment of valid
V CC , the RST and RST are excellent control signals for a µP.
The reset outputs will remain in their active states until V CC
has been continuously in–tolerance for a minimum of 250
msec allowing the power supply and µP to stabilize before
RST is released.
Push–button Reset Input
forces the reset outputs into their active states. Once PB RST
has been low for a time, t PBD , the push–button delay time,
the reset outputs go active. The reset outputs remain in their
active states for a minimum of 250 msec after PB RST rises
above V IH (Figure 3).
the PB RST input. The debounced input ignores input pulses
less than 1 msec and is guaranteed to recognize pulses of
20 msec or greater. No external pull–up resistor is required
because the PB RST input has an internal pull–up to V CC of
approximately 100 µA.
Watchdog Timer
period, the watchdog timer function forces RST and RST
signals to the active state. The preset time period is
determined by the TD inputs to be 150 msec with TD
connected to ground, 600 msec with TD open, or 1200 msec
with TD connected to V CC , typical. The watchdog timer
starts timing out from the set time period as soon as RST and
RST are inactive. If a high–to–low transition occurs on the
ST input pin prior to time–out, the watchdog timer is reset
and begins to time–out again. If the watchdog timer is
allowed to time–out, then the RST and RST signals are
driven to the active state for 250 msec minimum (Figure 2).
must be in a section of software that is executed regularly so
the time between toggles is less than the watchdog time–out
period. One common technique controls the µP I/O line
from two sections of the program. The software might set the
The NCP1232 detects out–of–tolerance power supply
The debounced manual reset input (PB RST) manually
A mechanical push–button or active logic signal can drive
When the ST input is not stimulated for a preset time
The software routine that strobes ST is critical. The code
http://onsemi.com
NCP1232
4
I/O line high while operating in the foreground mode and set
it low while in the background or interrupt mode. If both
modes do not execute correctly, the watchdog timer issues
reset pulses.
Supply Monitor Noise Sensitivity
negative–going changes in V DD . Systems with an inordinate
amount of electrical noise on V DD (such as systems using
relays), may require a 0.01 µF or 0.1 µF bypass capacitor to
reduce detection sensitivity. This capacitor should be
installed as close to the NCP1232 as possible to keep the
capacitor lead length short.
3–TERMINAL
REGULATOR
The NCP1232 is optimized for fast response to
0.1 µF
Figure 2. Watchdog Timer
Figure 1. Push–button Reset
+5 V
+5 V
V CC
PB RST
GND
NCP1232
V CC
TD
TOL
NCP1232
TD
RST
ST
TOL
GND
RST
ST
MICRO–
I/O
PROCESSOR
RESET
+5 V
10 KΩ
MICRO–
PROCESSOR
I/O
RESET