ncp1282 ON Semiconductor, ncp1282 Datasheet
ncp1282
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ncp1282 Summary of contents
Page 1
... High Performance Active Clamp/Reset PWM Controller Featuring 500 V Startup The NCP1282 is a voltage mode controller designed for ac-dc or dc-dc converters requiring high-efficiency and low parts count. This controller incorporates two in phase outputs with an overlap delay to prevent simultaneous conduction and facilitates soft switching. The main output is designed for driving a forward converter primary MOSFET ...
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... REF C SYNC T I CSKIP(C) 12 CSKIP C CSKIP I CSKIP( Clock Soft-Stop Complete Soft-Start V REF Soft-Stop Control Logic 10 I SS( SS(D) NCP1282 V - AUX(on One Shot + 1 V Pulse Thermal V Shutdown STOP Clock CSKIP Comparator + Saturation Comparator - + V CSKIP - CSKIP Control Saturated Logic Clock Ilimit Comparator - ...
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... The outputs are disabled during the C charge time. 7 SYNC Proprietary bidirectional frequency synchronization architecture allows two NCP1282 devices to syn‐ chronize together. The lower frequency device becomes the slave. It can also synchronize to an external signal Precision 5 ...
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... Human Body Model 2000 V per MIL–STD–883, Method 3015. Machine Model Method 160 V. Pin 1 is the HV startup of the device and is rated to the max rating of the part, or 500 V. 2. This device contains Latchup protection and exceeds "100 mA per JEDEC Standard JESD78. NCP1282 Rating http://onsemi.com 4 ...
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... Offset Current Turn ON Threshold ("5%, I LINE FEEDFORWARD Peak Voltage (Volt-Second Clamp) Discharge Current ( Offset Voltage ( Ramp Down Feedforward Offset Minus Soft-Stop Reset Voltage 3. Guaranteed by design only. NCP1282 ( 2 AUX UVOV EA = 0.01 mF 100 pF, C out1 out2 UVOV = 25° ...
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... J Peak Voltage ("3%) Valley Voltage ("3%) Discharge Current (V = 2.3 V) RTCT Maximum Operating Frequency (Note 4) Duty Cycle ( kW) D Adjustable Maximum Duty Cycle (Note 4) 4. Guaranteed by design only. NCP1282 (continued AUX UVOV = 10 mF 470 pF 100 pF out1 out2 = 29 ...
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... OUT2 Fall Time (90 2200 pF, C out1 OUT1 OUT2 PWM COMPARATOR Input Resistance Lower Input Threshold Delay to Output (From Guaranteed by design only. NCP1282 (continued AUX UVOV = 10 mF 470 pF 100 pF out1 out2 = 29.4 kW 470 pF ...
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... 0.2 V AUX AUX(on -50 - JUNCTION TEMPERATURE (°C) J Figure 4. Startup Current vs. Junction Temperature 100 NCP1282 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 100 125 150 -50 -25 Figure 3. Auxiliary Supply Voltage Thresholds 100 ...
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... J Figure 9. Line Under/Overvoltage Thresholds vs. Junction Temperature -50 - JUNCTION TEMPERATURE (°C) J Figure 11. UVOV Offset Current vs. Junction Temperature NCP1282 8.0 7 AUX 7.0 6.5 = 100 pF 6.0 5.5 5.0 4.5 4.0 3.5 3.0 100 125 150 10 11 Figure 8. Supply Current vs. Supply Voltage 150 140 130 120 ...
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... T , JUNCTION TEMPERATURE (°C) J Figure 15. Current Limit Threshold Voltage vs. Junction Temperature 100 -50 NCP1282 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 100 125 150 -50 -25 T Figure 14. Feedforward Peak Voltage 150 140 130 120 110 100 ...
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... UVOV 2.5 V REF 0 -50 - JUNCTION TEMPERATURE (°C) J Figure 22. V Discharge Current REF vs. Junction Temperature NCP1282 1.25 V CSKIP 100 125 150 -50 -25 Figure 19. Cycle Skip Discharge Current 5.25 1.0 5.20 0.9 0.8 5.15 0.7 5.10 5.05 0.6 5.00 0.5 0.4 4 ...
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... Figure 26. Duty Cycle vs. Junction Temperature 500 450 400 350 300 TRAILING 250 200 LEADING 150 100 160 240 R , DELAY RESISTOR (kW) D Figure 28. Overlap Time Delay vs. Delay Resistor NCP1282 470 pF AUX 25° ...
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... Figure 30. Output 1 Drive Resistance vs. Junction Temperature -50 - JUNCTION TEMPERATURE (°C) J Figure 32. V Input Resistance EA vs. Junction Temperature NCP1282 AUX SOURCE 100 125 150 -50 -25 T Figure 31. Output 2 Drive Resistance 1.5 1 ...
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... The NCP1282 is a voltage mode controller designed for ac-dc or dc-dc converters requiring high-efficiency and low parts count. This controller incorporates two in phase outputs with an adjustable overlap delay. The main output is designed for driving a forward converter primary MOSFET. The secondary output is designed for driving an active clamp circuit MOSFET, a synchronous rectifier on the secondary side asymmetric half bridge circuit ...
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... CS pin higher than V Instead of using a higher voltage threshold to detect a cycle skip fault, the NCP1282 uses a timer. It monitors the current cycle-by-cycle current limit condition exists the converter is disabled. The time to disable the converter and the time ...
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... REF current pulse and also add cost and complexity. The NCP1282 uses LEB circuitry that blocks out the first 70 ns (typ) of each current pulse. This removes the leading edge spikes without altering the current waveform. The blanking ...
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... V UVOV V REF out1 The startup regulator is disabled by biasing This feature allows the NCP1282 to operate from AUX(on) an independent 12 V supply. If operating from an independent supply, the V and V in connected together. The independent supply should maintain V above V . Otherwise, the Output AUX ...
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... UVOV pin to GND to prevent oscillation of the UVOV pin and filter line transients. Line Feedforward The NCP1282 incorporates line feedforward (FF) to limit the maximum volt-second product the line voltage times the ON time. This limit prevent saturation of the transformer in forward and flyback topologies. Another advantage of feedforward is a controller frequency gain independent of line voltage ...
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... V way to GND. The outputs are enabled if the V approximately 0.5 V above the valley of the FF Ramp. Outputs The NCP1282 has two in-phase output drivers with an adjustable overlap delay (t ). The main output, OUT1, has D a source resistance of 4.0 W (typ) and a sink resistance of 2 ...
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... This allows the user to optimize the delay for the turn on transition of the main switch and ensure the active clamp switch always exhibits zero volt switching. Analog and Power Ground (PGND) The NCP1282 has an analog ground, GND, and a power ground, PGND, terminal. GND is used for analog connections such ...
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... MASTER CONTROLLER Figure 50. Master-Slave Configuration 5.0 V Reference The NCP1282 has a precision 5.0 V reference output buffered version of the internal reference. The 5.0 V reference is biased directly from V to 5.0 mA. Load regulation and line regulation is 100 mV within the specified operating range required to bypass the reference with a capacitor. ...
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... PL 0.25 (0.010 The products described herein (NCP1282), may be covered by one or more of the following U.S. patents: 6,771,138. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “ ...