ncp1001 ON Semiconductor, ncp1001 Datasheet - Page 8
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ncp1001
Manufacturer Part Number
ncp1001
Description
Integrated Off-line Switching Regulator
Manufacturer
ON Semiconductor
Datasheet
1.NCP1001.pdf
(16 pages)
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Introduction
of integration by providing on a single monolithic chip all of
the active power, control, logic, and protection circuitry
required to implement a high voltage flyback or forward
converter. This device series is designed for direct operation
from a rectified 240 Vac line source and requires minimal
external components for a complete cost sensitive converter
solution. Potential markets include office automation,
industrial, residential, personal computer, and consumer. A
description of each of the functional blocks is given below,
and the representative block diagram is shown in Figure 17.
Oscillator
alternately gate on and off a trimmed current source and
current sink which are used to respectively charge and
discharge an on−chip timing capacitor between two voltage
levels. This configuration generates a precise linear
sawtooth ramp signal that is used to pulse width modulate
the MOSFET of the Power Switch circuit. During the charge
of the timing capacitor, the Oscillator duty cycle output
holds one input of the Driver low. This action keeps the
MOSFET of the Power Switch Circuit off, thus limiting the
maximum duty cycle. The Oscillator frequency is internally
programmed for 100 kHz operation with a controlled charge
to discharge current ratio that yields a maximum Power
Switch Circuit duty cycle of 72%. The Oscillator
temperature characteristics are shown in Figure 7.
PWM Comparator and Latch
comparator with the Oscillator ramp output applied to the
inverting input. The Oscillator clock output applies a set
pulse to the PWM Latch when the timing capacitor reaches
its peak voltage, initiating Power Switch Circuit conduction.
As the timing capacitor discharges, the ramp voltage
decreases to a level that is less than the Error Amplifier
output, causing the PWM Comparator to reset the latch and
terminate Power Switch Circuit conduction for the duration
of the ramp−down period. This method of having the
Oscillator set and the PWM Comparator reset the Latch
prevents the possibility of multiple output pulses during a
given Oscillator clock cycle. This circuit configuration is
commonly referred to as double pulse suppression logic. A
timing diagram is shown in Figure 18 that illustrates the
behavior of the pulse width modulator.
to operate between 73% and 0% duty cycle. The ability to
operate down to zero duty cycle allows for no load operation
without the burden of preloads. This feature is consistent
with the Blue Angle requirements, as it minimizes power
The NCP1000 thru NCP1002 represent a new higher level
The Oscillator block consists of two comparators that
The pulse width modulator (PWM) consists of a
No load operation. The pulse width modulator is designed
NCP1000, NCP1001, NCP1002
OPERATING DESCRIPTION
http://onsemi.com
8
consumption while in the stand−by operation mode. For
operation at no load, the output may skip cycles. This is a
common occurrence for this type of control circuit. The
converter will switch for several cycles, and due to delays in
the output filter and feedback loop, the duty cycle will not
be reduced until the output has exceeded it’s regulation limit.
The unit will then shut down for several cycles until the
voltage is below the regulation limit, and then it will switch
again. During the time that switching cycles are not present
the output voltage will decay according to it’s RC time
constant, which is based on the output capacitance and
internal loading from the regulation circuitry. During this
interval, the voltage on the V
decays below the lower hysteretic turn off threshold, the unit
will shut down and recycle. This mode of operation is not
normally desirable. In order to avoid it, the time constant
for the V
than the time constant of the output. If no load operation
is not required, a relatively small value (t10 mF) for the
V
Feedback Input
feeds the non−inverting input to the PWM. Pin 2 has a
nominal 2.7 kW internal resistor to ground, which converts
the optocoupler current into a voltage. Its’ signal is filtered
by a 7.0 kHz low pass filter which reduces high frequency
noise to the input of the PWM comparator.
connected between V
(pin 2). The photo transistor is effectively a current source
which is driven by the LED, which is connected to the output
regulation circuit of the power supply. An external capacitor
may be connected from pin 2 to ground for additional noise
filtering if necessary.
the ramp signal, the output of the power converter will be
operating at full duty cycle. The input current vs. duty cycle
transfer function is shown in Figure 2. As the voltage
increases, the duty cycle will vary linearly with the change
in voltage at the feedback input, between the upper and
lower extremes of the ramp waveform 2.7 V to 4.1 volts.
Above the upper extreme point of the ramp, the duty cycle
will be zero and no power will be transmitted to the output.
is low, the optocoupler will be off, leaving the voltage at
pin 2 at ground (full duty cycle). As the output voltage
increases, the optocoupler will begin to conduct, such that
the voltage at pin 2 increases until the proper duty cycle is
reached to maintain regulation.
diode to ground.
CC
The feedback input, pin 2, accepts the DC error signal that
Typically, the photo transistor of the optocoupler is
When the feedback input is below the lower threshold of
The circuit should be designed such that when the output
Pin 2 is protected from ESD transients by a 10 volt Zener
capacitor is acceptable.
CC
cap and load should be equal to, or greater
CC
(pin 1) and the Feedback input
CC
supply will also decay. If it