ice3ar4780jz Infineon Technologies Corporation, ice3ar4780jz Datasheet - Page 9

• Manufacturer Part Number: ice3ar4780jz
• Description: Off-line Smps Current Mode Controller With Integrated 800v Coolmos And Startup Cell Brownout & Frequency Jitter In Dip- 7
• Manufacturer: Infineon Technologies Corporation

When Active Burst Mode is entered, the internal Bias is
switched off most of the time but the Voltage Reference is
kept alive in order to reduce the current consumption below
620µA.
3.3
Figure 4
Current Mode means the duty cycle is controlled by the slope
of the primary current. This is done by comparing the FBB
signal with the amplified current sense signal.
Figure 5
Version 2.0
FBB
FBB
Driver
Amplified Current Signal
0.6V
Soft-Start Comparator
Improved Current Mode
Improved
Current Mode
Current Mode
Pulse Width Modulation
0.6V
t
PWM OP
on
C8
x3.25
PWM-Latch
R
S
CS
Q
Q
Driver
t
t
9
In case the amplified current sense signal exceeds the FBB
signal the on-time t
PWM-Latch (Figure 5).
The primary current is sensed by the external series resistor
R
means of Current Mode regulation, the secondary output
voltage is insensitive to the line variations. The current
waveform slope will change with the line variation, which
controls the duty cycle.
The external R
maximum source current of the integrated CoolMOS
To improve the Current Mode during light load conditions
the amplified current ramp of the PWM-OP is superimposed
on a voltage ramp, which is built by the switch T2, the
voltage source V1 and a resistor R1 (see Figure 6). Every
time the oscillator shuts down for maximum duty cycle
limitation the switch T2 is closed by V
oscillator triggers the Gate Driver, T2 is opened so that the
voltage ramp can start.
Figure 6
In case of light load the amplified current ramp is too small
to ensure a stable regulation. In that case the Voltage Ramp
is a well defined signal for the comparison with the FBB-
signal. The duty cycle is then controlled by the slope of the
Voltage Ramp.
By means of the time delay circuit which is triggered by the
inverted V
reaches approximately 156ns delay time (Figure 7). It allows
the duty cycle to be reduced continuously till 0% by
decreasing V
Sense
FBB
Oscillator
inserted in the source of the integrated CoolMOS
Voltage Ramp
Soft-Start Comparator
V
OSC
OSC
FBB
Improved Current Mode
T
signal, the Gate Driver is switched-off until it
Sense
2
below that threshold.
on
allows an individual adjustment of the
of the driver is finished by resetting the
circuit (156ns)
time delay
10kΩ
PWM Comparator
R
Functional Description
1
CoolSET
0.6V
C8
ICE3AR4780JZ
V
PWM-Latch
1
Gate Driver
PWM OP
OSC
X3.25
26 Aug 2010
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