ice2qr0665z Infineon Technologies Corporation, ice2qr0665z Datasheet - Page 9

• Manufacturer Part Number: ice2qr0665z
• Description: Of F -line Smps Quasi -resonant Pwm Cont Rol Ler Wi Th Integrated 650v Coolmos And Startup Cell In Dip-7
• Manufacturer: Infineon Technologies Corporation

the detected zero-crossing to the switch-on of the main
switch t
This time delay should be matched by adjusting the
time constant of the RC network which is calculated as:
3.3.1.3
After MOSFET is turned off, there will be some
oscillation on V
on ZC pin. To avoid mistriggering by such oscillations
to turn on the MOSFET, a ringing suppression timer is
implemented. This suppresion time is depended on the
voltage v
threshold V
However, if the voltage v
a shorter time is set.
3.3.1.4
After the gate drive goes to low, it can not be changed
to high during ring suppression time.
After ring suppression time, the gate drive can be
turned on when the ZC counter value is higher or equal
to up/down counter value.
However, it is also possible that the oscillation between
primary inductor and drain-source capacitor damps
very fast and IC can not detect enough zero crossings
and ZC counter value will not be high enough to turn on
the gate drive. In this case, a maximum off time is
implemented. After gate drive has been remained off
for the period of T
again regardless of the counter values and V
function
frequency from going lower than 20kHz. Otherwise it
will cause audible noise, during start up.
3.3.2
In the converter system, the primary current is sensed
by an external shunt resistor, which is connected
between low-side terminal of the main power switch
and the common ground. The sensed voltage across
the shunt resistor v
measurement unit, and its output voltage V
compared with the regulation voltage V
voltage V
is reset. As a result, the main power switch is switched
off. The relationship between the V
described by:
Version 2.0
Dt
t
V
td
1
=
=
=
T
------------ t
C
delay
osc
3.3 V
4
zc
1
ZC
can
exceeds the voltage V
×
, theoretically:
×
–
Ringing suppression time
Switch on determination
Switch Off Determination
. If the voltage v
-------------------------------- -
R
ZCRS
R
cs
delay
zc1
zc1
DS
+
, a longer preset time is applied.
effectively
, which will also appear on the voltage
OffMax
+
0.7
×
R
CS
R
zc2
zc2
is applied to an internal current
, the gate drive will be turned on
ZC
is higher than the threshold,
prevent
ZC
FB
is lower than the
, the output flip-flop
1
and the V
the
FB
. Once the
switching
ZC
. This
CS
1
[2]
[3]
[4]
is
is
9
To avoid mistriggering caused by the voltage spike
across the shunt resistor at the turn on of the main
power switch, a leading edge blanking time, t
applied to the output of the comparator. In other words,
once the gate drive is turned on, the minimum on time
of the gate drive is the leading edge blanking time.
In addition, there is a maximum on time, t
limitation implemented in the IC. Once the gate drive
has been in high state longer than the maximum on
time, it will be turned off to prevent the switching
frequency from going too low because of long on time.
3.4
There is a cycle by cycle current limitation realized by
the current limit comparator to provide an overcurrent
detection. The source current of the MOSFET is
sensed via a sense resistor R
source current is transformed to a sense voltage V
which is fed into the pin CS. If the voltage V
an internal voltage limit, adjusted according to the
Mains voltage, the comparator immediately turns off
the gate drive.
To prevent the Current Limitation process from
distortions caused by leading edge spikes, a Leading
Edge Blanking time (t
sensing path.
A further comparator is implemented to detect
dangerous current levels (V
one or more transformer windings are shorted or if the
secondary diode is shorted. To avoid an accidental
latch off, a spike blanking time of t
the output path of the comparator.
3.4.1
When the main bus voltage increases, the switch on
time becomes shorter and therefore the operating
frequency is also increased. As a result, for a constant
primary current limit, the maximum possible output
power is increased which is beyond the converter
design limit.
To avoid such a situation, the internal foldback point
correction circuit varies the V
to the bus voltage. This means the V
decreased when the bus voltage increases. To keep a
constant maximum input power of the converter, the
Current Limitation
Foldback Point Correction
LEB
Functional Description
) is integrated in the current
CSSW
CS
CS
voltage limit according
CoolSET
. By means of R
) which could occur if
ICE2QR0665Z
CSSW
March 17, 2011
is integrated in
CS
CS
®
exceeds
will be
- Q1
LEB
CS
OnMax
, is
the
CS
,