lt3692a Linear Technology Corporation, lt3692a Datasheet - Page 8
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lt3692a
Manufacturer Part Number
lt3692a
Description
Monolithic Dual Tracking 3.5a Step-down Switching Regulator
Manufacturer
Linear Technology Corporation
Datasheet
1.LT3692A.pdf
(40 pages)
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PIN FUNCTIONS
LT3692A
BST1/BST2: The BST pin provides a higher than V
drive to the power NPN to ensure a low switch drop. If the
voltage between the BST pin and the V
the voltage required to fully turn on the power NPN, the
power switch is turned off to recharge the BST capacitor.
CMPI1/CMPI2: The CMPI pin is an input to a compara-
tor with a threshold of 720mV and 60mV of hysteresis.
Connecting the CMPI pin to the FB pin will generate a
power good signal when the output is within 90% of its
regulated value.
CMPO1/CMPO2: The CMPO pin is an open-collector
output that sinks current when the CMPI pin falls below
its threshold. For a typical input voltage above 2.8V, its
output state remains true, although during shutdown, V
undervoltage lockout or thermal shutdown, its current sink
capability is reduced. The COMPO pins can be left open
circuit or tied together to form a single power good signal.
DIV: The voltage present at the DIV pin determines the ratio
of channel 1 frequency to the master clock frequency set
by the RT/SYNC pin. The DIV pin is driven by an internal
current source with a typical value of 12μA which allows
a single resistor from the DIV pin to ground to set the
DIV voltage and resulting channel 1 frequency divider.
Ratios of 1, 2, 4 and 8 are available. See the Applications
Information section for more information.
DNC: Do Not Connect.
GND: The exposed pad pin is the only ground connec-
tion for the device. The exposed pad should be soldered
to a large copper area to reduce thermal resistance. The
GND pin is common to both channels and also serves as
small-signal ground. For ideal operation all small-signal
ground paths should connect to the GND pin at a single
point avoiding any high current ground returns.
FB1/FB2: The FB pin is the negative input to the error am-
plifier. The output switches to regulate this pin to 806mV
with respect to the exposed ground pad. Bias current
flows out of the FB pin.
8
IN
pin is less than
IN
base
IN1
ILIM1/ILIM2: The voltage present at the ILIM pin deter-
mines the peak inductor current for the channel. The ILIM
pin is driven by an internal current source with a typical
value of 12μA. A resistor from the ILIM pin to ground sets
the ILIM voltage. The maximum current limit range is 4.8A
to 2A when the ILIM voltages are 1.5V and 0V respectively.
IND1/IND2: The IND pin is the input to the internal sense
resistor that measures current flowing in the inductor.
When the current in the resistor exceeds the current dic-
tated by the V
the output switch. Bias current flows out of the IND pin.
RT/SYNC: The voltage present at the RT/SYNC pin deter-
mines the constant switching frequency. The RT/SYNC
pin is driven by an internal current source with a typical
value of 12μA which allows a single resistor from the RT/
SYNC pin to ground to set the RT/SYNC voltage and result-
ing switching frequency. Minimum switching frequency
is typically 110kHz when V
switching frequency is typically 2.5MHz when V
is above 950mV.
Driving the RT/SYNC pin with an external clock signal will
synchronize the switch to the applied frequency. Synchro-
nization occurs on the rising edge of the clock signal after
the clock signal is detected. Each rising clock edge initiates
an oscillator ramp reset. A gain control loop servos the
oscillator charging current to maintain constant oscillator
amplitude. Hence, the slope compensation and channel
phase relationship remain unchanged. If the clock signal
is removed, the oscillator reverts to resistor mode after
the synchronization detection circuitry times out. The clock
source impedance should be set such that the current out
of the RT/SYNC pin in resistor mode generates a frequency
roughly equivalent to the synchronization frequency. See
the Applications Information section for more information.
C
pin, the SW latch is held in reset, disabling
RT/SYNC
is 0V and maximum
RT/SYNC
3692af