lt3695 Linear Technology Corporation, lt3695 Datasheet - Page 9

• Manufacturer Part Number: lt3695
• Description: 1a Fault Tolerant Micropower Step-down Regulator
• Manufacturer: Linear Technology Corporation

PIN FUNCTIONS
PGND (Pin 1): This is the power ground used by the catch
diode (D1 in the Block Diagram) when its anode is con-
nected to the DA pin.
DA (Pin 2): Connect the anode of the catch diode (D1)
to this pin. Internal circuitry senses the current through
the catch diode providing frequency foldback in extreme
situations.
NC (Pins 3, 10, 12): No Connects. These pins are not
connected to internal circuitry and must be left fl oating
to ensure fault tolerance.
SW (Pin 4): The SW pin is the output of the internal power
switch. Connect this pin to the inductor, catch diode and
boost capacitor.
RUN/SS (Pin 5): The RUN/SS pin is used to put the LT3695
in shutdown mode. Tie to ground to shut down the LT3695.
Tie to 2.5V or more for normal operation. RUN/SS also
provides a soft-start function; see the Applications Infor-
mation section for more information.
RT (Pin 6): Oscillator Resistor Input. Connect a resistor
from this pin to ground to set the switching frequency.
SYNC (Pin 7): This is the external clock synchronization
input. Ground this pin with a 100k resistor for low ripple
Burst Mode operation at low output loads. Tie to 0.8V or
more for pulse-skipping mode operation. Tie to a clock
source for synchronization. Clock edges should have rise
and fall times faster than 1μs. Note that the maximum
load current depends on which mode is chosen. See the
Applications Information section for more information.
V
regulator and to the internal power switch. This pin must
be locally bypassed.
V
amplifi er. The voltage on this pin controls the peak switch
current. Tie an RC network from this pin to ground to
compensate the control loop.
FB (Pin 11): The LT3695 regulates the FB pin to 0.8V. Con-
nect the feedback resistor divider tap to this pin.
PG (Pin 13): The PG pin is the open-collector output of
an internal comparator. PG remains low until the FB pin
is within 10% of the fi nal regulation voltage. PG output is
valid when V
RUN/SS is high.
GND (Pin 14): The GND pin is the ground of all the internal
circuitry. Tie directly to the local GND plane.
BD (Pin 15): This pin connects to the anode of the boost
Schottky diode and also supplies current to the LT3695’s
internal regulator.
BOOST (Pin 16): This pin is used to provide a drive volt-
age, higher than the input voltage, to the internal bipolar
NPN power switch. Connect a capacitor (typically 0.22μF)
between BOOST and SW.
Exposed Pad (Pin 17): PGND. This is the power ground
used by the catch diode (D1) when its anode is connected
to the DA pin. The Exposed Pad may be soldered to the
PCB in order to lower the thermal resistance.
IN
C
(Pin 9): The V
(Pin 8): The V
IN
is above the minimum input voltage and
C
IN
pin is the output of the internal error
pin supplies current to the internal
LT3695
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