mx8830 Clare, Inc., mx8830 Datasheet - Page 3

• Manufacturer Part Number: mx8830
• Description: Synchronous Buck Mosfet Driver
• Manufacturer: Clare, Inc.

Lead / Signal Description and Configurations
SOIC and DFN Top View Lead Configurations
MX8830
Drawing No. 0883009
MX8830B
N/A
N/A
N/A
N/A
1
2
3
4
5
6
7
8
MX8830R
N/A
N/A
10
2
3
5
6
7
8
9
4
1
Bonding Pad
Bonding Pad
Bonding Pad
Bonding Pad
Bonding Pad
Bonding Pad
Bonding Pad
Bonding Pad
Bonding Pad
Bonding Pad
Bonding Pad
Bonding Pad
MX8830X
AGND
PGND
PRDY
Name
PWM
HGD
VDD
LGD
BST
DLY
LSD
SW
___
SD
__
3
Description
Upper Gate Driver Floating DC Power Terminal for
Bootstrap Capacitor Connection.
Analog Ground
Three State PWM Input. PWM input to the Gate Drivers.
Positive Supply Terminal for Logic and Lower Gate
Driver. A ceramic bypass capacitor of 1uF should be
connected from VDD to PGND.
Lower Gate Driver Output Terminal
Lower Gate Driver DC Power Return Terminal
Upper Gate Driver Floating DC Power Return Terminal
Upper Gate Driver Output Terminal
Terminal for External Delay Capacitor Connection.
Capacitor to Ground at this pin adds propagation delay
from Lower Gate Driver going Low to the Upper Gate
Driver going High.
t
TTL-level Shut Down Input Signal with active pull-up.
SD
the driver outputs are forced low and I
minimum.
TTL-level Low Side Shut Down Input Signal with active
pull-up.
output low.
When LSD is high, the lower Gate Driver output is
enabled.
Power Good Output Terminal. Logic high at this terminal
indicates VDD is above the UVLO Threshold.
DLY
enables normal operation when high. When
(nS) = C
LS , when low forces the Lower Gate Driver
MX8830B/MX8830R/MX8830X
D
DLY
(pF) x (0.5nS/pF)
DD
www.claremicronix.com
is at its
SD
is low,
8/9/07