ncp5214 ON Semiconductor, ncp5214 Datasheet - Page 21

• Manufacturer Part Number: ncp5214
• Description: 2-in-1 Notebook Ddr Power Controller
• Manufacturer: ON Semiconductor

MOSFETs used in buck converter should be at least 1.2 times
of the maximum input voltage. Generally, V
should be sufficient for both high−side MOSFET and
low−side MOSFET of the buck converter for notebook
application.
smaller; the better is the MOSFET while R
enough. MOSFETs are susceptible to false turn−on under
high dV/dt and high VDS conditions. Under high dV/dt and
high V
the capacitor divider formed by C
C
the threshold voltage, the MOSFET will turn on.
Therefore, it should be checked that the low−side MOSFET
have low Q
MOSFET have better immunity to short moment false
turn−on due to high dV/dt during the turn−on of the
high−side MOSFET. Such short moment false turn−on will
cause minor shoot−through current which will degrade
efficiency, especially at high input voltage condition.
Overcurrent Protection of VDDQ Buck Regulator
the current flowing through the high−side FET and
inductor during S0 and S3. The overcurrent tripping level
is programmed by an external resistor RL1 connected
between the OCDDQ pin and drain of the high−side FET.
An internal 31 mA current sink (IOC) at pin OCDDQ
establishes a voltage drop across the resistor RL1 at a
magnitude of RL1xIOC and develops a voltage at the
non−inverting input of the current limit comparator.
Another voltage drop is established across the high−side
MOSFET R
voltage is developed at SWDDQ when the high−side
MOSFET is turned on and the inductor current flows
through the R
non−inverting input of the current limit comparator is then
compared to the voltage at SWDDQ pin when the
high−side gate drive is high after a fixed period of blanking
time (150 ns) to avoid false current limit triggering. When
the voltage at SWDDQ is lower than the voltage at the
non−inverting input of the current limit comparator for four
consecutive internal clock cycles, an overcurrent condition
occurs, during which, all outputs will be latched off to
protect against a short−to−ground condition on SWDDQ or
VDDQ. i.e., the voltage drop across the R
high−side FET developed by the drain current is larger than
the voltage drop across RL1, the OCP is triggered and the
device will be latched off.
current hit the I
high to VIN through a resistor RL1 and this pin cannot be
GS
The maximum drain−to−source voltage rating of the
As a general rule of thumb, the gate charges are the
The OCP circuit is configured to set the current limit for
The overcurrent protection will trip when a peak inductor
It should be noted that the OCDDQ pin must be pulled
to charge up and the V
DS
condition, current will flow through the C
GD
DS(on)
DS(on)
to Q
LIMIT
I LIMIT + RL1
GS
at a magnitude of I
of the MOSFET. The voltage at the
ratio. This indicates that the low−side
determined by the equation:
GS
R DS(on)
to rise. If the V
GD
IOC
and C
L
DS(on)
xR
GS
GS
DS(on)
DSS
, cause the
rises above
is still low
DS(on)
of 30 V
(eq. 19)
http://onsemi.com
and a
GD
NCP5214
of
of
21
left floating for normal operation. The voltage drop across
RL1 must be less than 1.0 V to allow enough headroom for
the voltage detection at the OCDDQ pin under low VIN
condition. In addition, since the MOSFET R
with temperature as current flows through the MOSFET
increases, the OCP trip point also varies with the MOSFET
R
MOSFET R
triggering the overcurrent protection in normal operating
output load range, calculate the RL1 value from the
previous equation with the following conditions such that
minimum value of inductor current limit is set:
closed to the lead of the current limit setting resistor RL1
which connected to the drain of the high−side MOSFET.
Loop Compensation
determined, the compensation network components can be
selected. Since NCP5214 is a voltage mode PWM
converter with output LC filter, Type III compensation
network is required to obtain the desired close loop
bandwidth and phase boost with unconditional stability.
The NCP5214 PWM modulator, output LC filter and
Type III compensation network are shown in Figure 39.
The output LC filter has a double pole and a single zero.
The double pole is due to the inductance of the inductor and
capacitance of the output capacitor, while the single zero
is due to the ESR and capacitance of the output capacitor.
The Type III compensation has two RC pole−zero pairs.
The two zeros are used to compensate the LC double pole
and provide 180° phase boost. The two poles are used to
compensate the ESR zero and provide controlled gain
roll−off. For an ideally compensated system, the Bode plot
should have the close−loop gain roll−off with a slope of
−20 dB/decade crossing the 0 dB with the required
bandwidth and the phase margin larger than 45° for all
frequencies below the 0 dB frequency. The closed loop
gain is obtained by adding the modulator and filter gain (in
dB) to the compensation gain (in dB)
frequency at which the gain is 0 dB and the phase margin
is the difference between the close loop phase and 180°.
The goal of compensation is to achieve a stable close loop
system with the highest possible bandwidth, the gain
having −20 dB/decade slope at 0 dB gain crossing, and
sufficient phase margin for stability. The bandwidth of
close loop gain should be less than 50% of the switching
frequency and the compensation gain should be bounded
by the error amplifier open loop gain.
DS(on)
Since the IOC and R
Besides, a decoupling capacitor C
Once the output LC filter components have been
1. The minimum IOC value from the specification
2. The maximum R
3. Determine I
table.
the highest junction temperature.
I
I
L(ripple)/
VTT(max)
temperature variation.
DS(on)
2, where I
if VTT is powered by VDDQ.
increase with temperature, to avoid false
LIMIT
DS(on)
DS(on)
for I
LOAD(max)
LIMIT
have device variations and
of the MOSFET used at
> I
DCPL
.
= I
The bandwidth is the
LOAD(max)
VDDQ(max)
should be added
DS(on)
+
+
varies