ncp5203 ON Semiconductor, ncp5203 Datasheet - Page 7

• Manufacturer Part Number: ncp5203
• Description: 2-in-1 Ddr Power Controller
• Manufacturer: ON Semiconductor

General
the efficiency of a VDDQ PWM controller with the
simplicity of a linear regulator for VTT termination. Both
VDDQ and VTT outputs can be user adjusted.
voltage monitors, soft−start, VDDQ overvoltage and
undervoltage detection, supply undervoltage monitors, and
thermal shutdown, makes this device a total power solution
for high current DDR memory systems.
VDDQ Switching Regulator in Normal (S0) Mode
rectification buck controller directly driving two external
N−Channel power FETs. An external resistor divider sets
the nominal output voltage. The control architecture is
voltage mode fixed frequency PWM (300 kHz
with external compensation. The VDDQ output voltage is
divided down and fed back to the inverting input of an
internal amplifier through the FBDDQ pin to close the loop
at VDDQ = VFBDDQ
compares the feedback voltage with an internal VREF1
(= 1.25 V) to generate an error signal for the PWM
comparator. This error signal is further compared with a
VDDQ Regulator in Standby Mode (S3)
asynchronous switch mode. The switching frequency is
increased to 600 kHz, the low−side FET is disabled, and the
body diode of the low side FET is used. The regulator will
operate in discontinuous conduction mode (DCM) and the
switching frequency is doubled to reduce peak conduction
current.
VDDQ Regulator Fault Protection
current limit for the high−side switch. An internal 35 mA
current sink at OCDDQ pin establishes a voltage drop
Table 1. State, Operation, Input and Output Condition Table
The NCP5203 2−in−1 DDR Power Controller combines
The inclusion of both VDDQ and VTT power good
The VDDQ regulator is a switching synchronous
During
During S0 and S3, the external resistor (RL1) sets the
MODE
S5
S0
S3
S5
S3,
5VDUAL
UVLO
High
High
High
Low
the
VDDQ
USER INPUTS
(1 + R2/R1). This amplifier
VDDQEN
High
High
Low
X
regulator
DETAILED OPERATING DESCRIPTION
VTTEN
operates
High
Low
X
X
12.5%)
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NCP5203
OPERATING CONDITIONS
in
Standby
Normal
VDDQ
H−Z
H−Z
7
fixed frequency Ramp waveform derived from the internal
oscillator to generate a pulse−width−modulated signal.
This PWM signal drives the external N−Channel Power
FETs via the TGDDQ and BGDDQ pins. External inductor
L and capacitor COUT1 filter the output. The VDDQ
output voltage ramps up at a pre−defined soft−start rate
each time the IC exits S5. When in normal mode, and
regulation of VDDQ is detected, signal INREGDDQ will
go high to notify the control logic block.
used to eliminate the conduction loss contributed by the
forward voltage of a diode or Schottky diode rectifier.
Adaptive
complementary gate drive output signals is provided to
reduce shoot−through current.
Tolerance of VDDQ
resistor divider R2/R1 both impact the precision of VDDQ.
When the control loop is in regulation, VDDQ = VFBDDQ
VFBDDQ tolerance of 2%, a worst case range of 2.5% for
VDDQ will be assured if the ratio R2/R1 is specified as
0.98985 1%.
across this resistor. This voltage is compared to the voltage
at SWDDQ pin when the TGDDQ is high after a fixed
blanking period of 500 ns to avoid false current limit
triggering. When the voltage at SWDDQ is lower than
OCDDQ, an overcurrent condition occurs, upon which all
outputs will be latched off to protect against a
short−to−ground condition on SWDDQ or VDDQ. The IC
will be reset once 5VDUAL or VDDQEN is cycled.
VDDQ Regulator Feedback Compensation
Figure 2.
For enhanced efficiency, an active synchronous switch is
The tolerance of VFBDDQ and the ratio of the external
The recommended compensation network is shown in
(1 + R2/R1). With a worst case (overtemperature)
Normal
VTT
H−Z
H−Z
H−Z
non−overlap
(300 kHz)
(600 kHz)
TGDDQ
Normal
Normal
Low
Low
OUTPUT CONDITIONS
timing
(300 kHz)
BGDDQ
Normal
Low
Low
Low
control
PGOOD
H−Z
of
Low
Low
Low
the